Built-In Self-Test in a 24 Bit Floating Point Digital Signal Processor

Narumi SAKASHITA; Hisako SAWAI; Eiichi TERAOKA; Toshiki FUJIYAMA; Tohru KENGAKU; Yukihiko SHIMAZU; Akiharu TADA; Takeshi TOKUDA

Built-In Self-Test in a 24 Bit Floating Point Digital Signal Processor

Narumi SAKASHITA, Hisako SAWAI, Eiichi TERAOKA, Toshiki FUJIYAMA, Tohru KENGAKU, Yukihiko SHIMAZU, Akiharu TADA, Takeshi TOKUDA

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A built-in self-test (BIST) based on a signature-analysis (one of the data compression techniques) has been implemented in a 24 bit floating point digital signal processor (DSP). By using only a single pair of linear feedback shift registers (LFSR's) and 253 words of instruction of the DSP, 95% of the functional blocks are self-tested. The number of test patterns is 35 million. It takes only 2.6 seconds for the test at f_c26.7 MHz. The overhead of the BIST hardware is about 2.0% of the die size. By comparing the pass rate in a conventional function test to the BIST, nearly the same fault coverage is obtained. This result shows that the BIST is effective for VLSI processors, such as DSPs. By improving this method, manufacturing go/no-go tests without expensive test equipment will be possible.

Publication: IEICE TRANSACTIONS on Electronics Vol.E74-C No.11 pp.3838-3844

Publication Date: 1991/11/25

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Type of Manuscript: Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor)

Category: Dedicated Processors

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Narumi SAKASHITA
Hisako SAWAI
Eiichi TERAOKA
Toshiki FUJIYAMA
Tohru KENGAKU
Yukihiko SHIMAZU
Akiharu TADA
Takeshi TOKUDA

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Narumi SAKASHITA, Hisako SAWAI, Eiichi TERAOKA, Toshiki FUJIYAMA, Tohru KENGAKU, Yukihiko SHIMAZU, Akiharu TADA, Takeshi TOKUDA, "Built-In Self-Test in a 24 Bit Floating Point Digital Signal Processor" in IEICE TRANSACTIONS on Electronics, vol. E74-C, no. 11, pp. 3838-3844, November 1991, doi: .
Abstract: A built-in self-test (BIST) based on a signature-analysis (one of the data compression techniques) has been implemented in a 24 bit floating point digital signal processor (DSP). By using only a single pair of linear feedback shift registers (LFSR's) and 253 words of instruction of the DSP, 95% of the functional blocks are self-tested. The number of test patterns is 35 million. It takes only 2.6 seconds for the test at f_c26.7 MHz. The overhead of the BIST hardware is about 2.0% of the die size. By comparing the pass rate in a conventional function test to the BIST, nearly the same fault coverage is obtained. This result shows that the BIST is effective for VLSI processors, such as DSPs. By improving this method, manufacturing go/no-go tests without expensive test equipment will be possible.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e74-c_11_3838/_p

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@ARTICLE{e74-c_11_3838,
author={Narumi SAKASHITA, Hisako SAWAI, Eiichi TERAOKA, Toshiki FUJIYAMA, Tohru KENGAKU, Yukihiko SHIMAZU, Akiharu TADA, Takeshi TOKUDA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Built-In Self-Test in a 24 Bit Floating Point Digital Signal Processor},
year={1991},
volume={E74-C},
number={11},
pages={3838-3844},
abstract={A built-in self-test (BIST) based on a signature-analysis (one of the data compression techniques) has been implemented in a 24 bit floating point digital signal processor (DSP). By using only a single pair of linear feedback shift registers (LFSR's) and 253 words of instruction of the DSP, 95% of the functional blocks are self-tested. The number of test patterns is 35 million. It takes only 2.6 seconds for the test at f_c26.7 MHz. The overhead of the BIST hardware is about 2.0% of the die size. By comparing the pass rate in a conventional function test to the BIST, nearly the same fault coverage is obtained. This result shows that the BIST is effective for VLSI processors, such as DSPs. By improving this method, manufacturing go/no-go tests without expensive test equipment will be possible.},
keywords={},
doi={},
ISSN={},
month={November},}

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TY - JOUR
TI - Built-In Self-Test in a 24 Bit Floating Point Digital Signal Processor
T2 - IEICE TRANSACTIONS on Electronics
SP - 3838
EP - 3844
AU - Narumi SAKASHITA
AU - Hisako SAWAI
AU - Eiichi TERAOKA
AU - Toshiki FUJIYAMA
AU - Tohru KENGAKU
AU - Yukihiko SHIMAZU
AU - Akiharu TADA
AU - Takeshi TOKUDA
PY - 1991
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E74-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 1991
AB - A built-in self-test (BIST) based on a signature-analysis (one of the data compression techniques) has been implemented in a 24 bit floating point digital signal processor (DSP). By using only a single pair of linear feedback shift registers (LFSR's) and 253 words of instruction of the DSP, 95% of the functional blocks are self-tested. The number of test patterns is 35 million. It takes only 2.6 seconds for the test at f_c26.7 MHz. The overhead of the BIST hardware is about 2.0% of the die size. By comparing the pass rate in a conventional function test to the BIST, nearly the same fault coverage is obtained. This result shows that the BIST is effective for VLSI processors, such as DSPs. By improving this method, manufacturing go/no-go tests without expensive test equipment will be possible.
ER -