Technology Trends in ASIC

Nobuaki IEDA

Technology Trends in ASIC

Nobuaki IEDA

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Focusing on gate array and standard cell design LSIs, technology trends in ASIC are discussed. MOS transistors with LDD or modified LDD structures will be effective down to around 0.4 µm. Upon further miniaturization, simple single-drain structure MOS transistors will become prominent. SOI-structure MOS transistors may be even more effective with a smaller short channel effect. The supply voltage should be lowered to 3.3 V for 0.5 µm CMOS LSIs to decrease power dissipation owing to the increase of gate count and operation speed. SOG gate arrays will increase their share of the ASIC market. BiNMOS circuits will be useful under 5 V VDD condition. However, below 3.0 V, CMOS circuits will be preferable. In the near future, tpd of 20-30 ps/gate and 40-50 ps/gate should be attained for GaAs FET and Si-bipolar LSIs, respectively.

Publication: IEICE TRANSACTIONS on Electronics Vol.E74-C No.1 pp.148-156

Publication Date: 1991/01/25

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Nobuaki IEDA, "Technology Trends in ASIC" in IEICE TRANSACTIONS on Electronics, vol. E74-C, no. 1, pp. 148-156, January 1991, doi: .
Abstract: Focusing on gate array and standard cell design LSIs, technology trends in ASIC are discussed. MOS transistors with LDD or modified LDD structures will be effective down to around 0.4 µm. Upon further miniaturization, simple single-drain structure MOS transistors will become prominent. SOI-structure MOS transistors may be even more effective with a smaller short channel effect. The supply voltage should be lowered to 3.3 V for 0.5 µm CMOS LSIs to decrease power dissipation owing to the increase of gate count and operation speed. SOG gate arrays will increase their share of the ASIC market. BiNMOS circuits will be useful under 5 V VDD condition. However, below 3.0 V, CMOS circuits will be preferable. In the near future, tpd of 20-30 ps/gate and 40-50 ps/gate should be attained for GaAs FET and Si-bipolar LSIs, respectively.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e74-c_1_148/_p

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@ARTICLE{e74-c_1_148,
author={Nobuaki IEDA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Technology Trends in ASIC},
year={1991},
volume={E74-C},
number={1},
pages={148-156},
abstract={Focusing on gate array and standard cell design LSIs, technology trends in ASIC are discussed. MOS transistors with LDD or modified LDD structures will be effective down to around 0.4 µm. Upon further miniaturization, simple single-drain structure MOS transistors will become prominent. SOI-structure MOS transistors may be even more effective with a smaller short channel effect. The supply voltage should be lowered to 3.3 V for 0.5 µm CMOS LSIs to decrease power dissipation owing to the increase of gate count and operation speed. SOG gate arrays will increase their share of the ASIC market. BiNMOS circuits will be useful under 5 V VDD condition. However, below 3.0 V, CMOS circuits will be preferable. In the near future, tpd of 20-30 ps/gate and 40-50 ps/gate should be attained for GaAs FET and Si-bipolar LSIs, respectively.},
keywords={},
doi={},
ISSN={},
month={January},}

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TY - JOUR
TI - Technology Trends in ASIC
T2 - IEICE TRANSACTIONS on Electronics
SP - 148
EP - 156
AU - Nobuaki IEDA
PY - 1991
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E74-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 1991
AB - Focusing on gate array and standard cell design LSIs, technology trends in ASIC are discussed. MOS transistors with LDD or modified LDD structures will be effective down to around 0.4 µm. Upon further miniaturization, simple single-drain structure MOS transistors will become prominent. SOI-structure MOS transistors may be even more effective with a smaller short channel effect. The supply voltage should be lowered to 3.3 V for 0.5 µm CMOS LSIs to decrease power dissipation owing to the increase of gate count and operation speed. SOG gate arrays will increase their share of the ASIC market. BiNMOS circuits will be useful under 5 V VDD condition. However, below 3.0 V, CMOS circuits will be preferable. In the near future, tpd of 20-30 ps/gate and 40-50 ps/gate should be attained for GaAs FET and Si-bipolar LSIs, respectively.
ER -