Two-Dimensional Device Simulation of 0.1 µm Thin-Film SOI MOSFET's

Hans-Oliver JOACHIM; Yasuo YAMAGUCHI; Kiyoshi ISHIKAWA; Norihiko KOTANI; Tadashi NISHIMURA; Katsuhiro TSUKAMOTO

Two-Dimensional Device Simulation of 0.1 µm Thin-Film SOI MOSFET's

Hans-Oliver JOACHIM, Yasuo YAMAGUCHI, Kiyoshi ISHIKAWA, Norihiko KOTANI, Tadashi NISHIMURA, Katsuhiro TSUKAMOTO

Full Text Views

0

Share
Cite this

Summary :

Thin- and ultra-thin-film SOI MOSFET's are promising candidates to overcome the constraints for future miniaturized devices. This paper presents simulation results for a 0.1 µm gate length SOI MOSFET structure using a two-dimensional/two-carrier device simulator with a nonlocal model for the avalanche induced carrier generation. For the suppression of punchthrough effect in devices with a channel doping of 1 10¹⁶ cm^-3 and 5 nm thick gate oxide it is found that the SOI layer thickness has to be reduced to at least 20 nm. The thickness of the buried oxide should not be smaller than 50 nm in order to avoid the degradation of thin SOI performance advantages. Investigating ways to suppress the degradation of the sub-threshold slope factor at these device dimensions it was found in contrast to the common expectation that the S-factor can be improved by increasing the body doping concentration. This phenomenon, which is a unique feature of thin-film depleted SOI MOSFET's, is explained by an analytical mode. At lower doping the area of the current flow is reduced by a decreasing effective channel thickness resulting in a slope factor degradation. Other approaches for S-factor improvement are the reduction of the channel edge capacitances by source/drain engineering or the decrease of SOI thickness or gate oxide thickness. For the latter approach a higher permittivity gate insulating material should be used in order to prevent tunnelling. The low breakdown voltage can be increased by utilizing an LDD structure to be suitable for a 1.5 V power supply. However, this is at the expense of reduced current drive. An alternative could be the supply voltage reduction to 1.0 V for single drain structure use. A dual-gated SOI MOSFET has an improved performance due to the parallel combination of two MOSFET's in this device. A slightly reduced breakdown voltage indicates a larger drain electric field present in this structure.

Publication: IEICE TRANSACTIONS on Electronics Vol.E75-C No.12 pp.1498-1505

Publication Date: 1992/12/25

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Special Issue on SOI (Si on Insulator) Devices)

Category: Deep Sub-micron SOI CMOS

Cite this

Copy

Hans-Oliver JOACHIM, Yasuo YAMAGUCHI, Kiyoshi ISHIKAWA, Norihiko KOTANI, Tadashi NISHIMURA, Katsuhiro TSUKAMOTO, "Two-Dimensional Device Simulation of 0.1 µm Thin-Film SOI MOSFET's" in IEICE TRANSACTIONS on Electronics, vol. E75-C, no. 12, pp. 1498-1505, December 1992, doi: .
Abstract: Thin- and ultra-thin-film SOI MOSFET's are promising candidates to overcome the constraints for future miniaturized devices. This paper presents simulation results for a 0.1 µm gate length SOI MOSFET structure using a two-dimensional/two-carrier device simulator with a nonlocal model for the avalanche induced carrier generation. For the suppression of punchthrough effect in devices with a channel doping of 1 10¹⁶ cm^-3 and 5 nm thick gate oxide it is found that the SOI layer thickness has to be reduced to at least 20 nm. The thickness of the buried oxide should not be smaller than 50 nm in order to avoid the degradation of thin SOI performance advantages. Investigating ways to suppress the degradation of the sub-threshold slope factor at these device dimensions it was found in contrast to the common expectation that the S-factor can be improved by increasing the body doping concentration. This phenomenon, which is a unique feature of thin-film depleted SOI MOSFET's, is explained by an analytical mode. At lower doping the area of the current flow is reduced by a decreasing effective channel thickness resulting in a slope factor degradation. Other approaches for S-factor improvement are the reduction of the channel edge capacitances by source/drain engineering or the decrease of SOI thickness or gate oxide thickness. For the latter approach a higher permittivity gate insulating material should be used in order to prevent tunnelling. The low breakdown voltage can be increased by utilizing an LDD structure to be suitable for a 1.5 V power supply. However, this is at the expense of reduced current drive. An alternative could be the supply voltage reduction to 1.0 V for single drain structure use. A dual-gated SOI MOSFET has an improved performance due to the parallel combination of two MOSFET's in this device. A slightly reduced breakdown voltage indicates a larger drain electric field present in this structure.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e75-c_12_1498/_p

Copy

@ARTICLE{e75-c_12_1498,
author={Hans-Oliver JOACHIM, Yasuo YAMAGUCHI, Kiyoshi ISHIKAWA, Norihiko KOTANI, Tadashi NISHIMURA, Katsuhiro TSUKAMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Two-Dimensional Device Simulation of 0.1 µm Thin-Film SOI MOSFET's},
year={1992},
volume={E75-C},
number={12},
pages={1498-1505},
abstract={Thin- and ultra-thin-film SOI MOSFET's are promising candidates to overcome the constraints for future miniaturized devices. This paper presents simulation results for a 0.1 µm gate length SOI MOSFET structure using a two-dimensional/two-carrier device simulator with a nonlocal model for the avalanche induced carrier generation. For the suppression of punchthrough effect in devices with a channel doping of 1 10¹⁶ cm^-3 and 5 nm thick gate oxide it is found that the SOI layer thickness has to be reduced to at least 20 nm. The thickness of the buried oxide should not be smaller than 50 nm in order to avoid the degradation of thin SOI performance advantages. Investigating ways to suppress the degradation of the sub-threshold slope factor at these device dimensions it was found in contrast to the common expectation that the S-factor can be improved by increasing the body doping concentration. This phenomenon, which is a unique feature of thin-film depleted SOI MOSFET's, is explained by an analytical mode. At lower doping the area of the current flow is reduced by a decreasing effective channel thickness resulting in a slope factor degradation. Other approaches for S-factor improvement are the reduction of the channel edge capacitances by source/drain engineering or the decrease of SOI thickness or gate oxide thickness. For the latter approach a higher permittivity gate insulating material should be used in order to prevent tunnelling. The low breakdown voltage can be increased by utilizing an LDD structure to be suitable for a 1.5 V power supply. However, this is at the expense of reduced current drive. An alternative could be the supply voltage reduction to 1.0 V for single drain structure use. A dual-gated SOI MOSFET has an improved performance due to the parallel combination of two MOSFET's in this device. A slightly reduced breakdown voltage indicates a larger drain electric field present in this structure.},
keywords={},
doi={},
ISSN={},
month={December},}

Copy

TY - JOUR
TI - Two-Dimensional Device Simulation of 0.1 µm Thin-Film SOI MOSFET's
T2 - IEICE TRANSACTIONS on Electronics
SP - 1498
EP - 1505
AU - Hans-Oliver JOACHIM
AU - Yasuo YAMAGUCHI
AU - Kiyoshi ISHIKAWA
AU - Norihiko KOTANI
AU - Tadashi NISHIMURA
AU - Katsuhiro TSUKAMOTO
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E75-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 1992
AB - Thin- and ultra-thin-film SOI MOSFET's are promising candidates to overcome the constraints for future miniaturized devices. This paper presents simulation results for a 0.1 µm gate length SOI MOSFET structure using a two-dimensional/two-carrier device simulator with a nonlocal model for the avalanche induced carrier generation. For the suppression of punchthrough effect in devices with a channel doping of 1 10¹⁶ cm^-3 and 5 nm thick gate oxide it is found that the SOI layer thickness has to be reduced to at least 20 nm. The thickness of the buried oxide should not be smaller than 50 nm in order to avoid the degradation of thin SOI performance advantages. Investigating ways to suppress the degradation of the sub-threshold slope factor at these device dimensions it was found in contrast to the common expectation that the S-factor can be improved by increasing the body doping concentration. This phenomenon, which is a unique feature of thin-film depleted SOI MOSFET's, is explained by an analytical mode. At lower doping the area of the current flow is reduced by a decreasing effective channel thickness resulting in a slope factor degradation. Other approaches for S-factor improvement are the reduction of the channel edge capacitances by source/drain engineering or the decrease of SOI thickness or gate oxide thickness. For the latter approach a higher permittivity gate insulating material should be used in order to prevent tunnelling. The low breakdown voltage can be increased by utilizing an LDD structure to be suitable for a 1.5 V power supply. However, this is at the expense of reduced current drive. An alternative could be the supply voltage reduction to 1.0 V for single drain structure use. A dual-gated SOI MOSFET has an improved performance due to the parallel combination of two MOSFET's in this device. A slightly reduced breakdown voltage indicates a larger drain electric field present in this structure.
ER -