In order to expect the single event occurrence on highly integrated CMOS memory circuit, quantitative evaluation of charge sharing between memory cells is needed. In this study, charge sharing area induced by heavy ion incident is quantitatively calculated by using device-simulation-based method. The validity of this method is experimentally confirmed using the charged heavy ion accelerator.

Cross sections that cause single event upsets by heavy ions are sensitive to doping concentration in the source and drain regions, and the structure of the raised source and drain regions especially in FDSOI. Due to the parasitic bipolar effect (PBE), radiation-hardened flip flops with stacked transistors in FDSOI tend to have soft errors, which is consistent with measurement results by heavy-ion irradiation. Device-simulation results in this study show that the cross section is proportional to the silicon thickness of the raised layer and inversely proportional to the doping concentration in the drain. Increasing the doping concentration in the source and drain region enhance the Auger recombination of carriers there and suppresses the parasitic bipolar effect. PBE is also suppressed by decreasing the silicon thickness of the raised layer. Cgg-Vgs and Ids-Vgs characteristics change smaller than soft error tolerance change. Soft error tolerance can be effectively optimized by using these two determinants with only a small impact on transistor characteristics.

The short-channel effect (SCE) in a MOSFET with an atomically thin MoS$_{2}$ channel was studied using a TCAD simulator. We derived the surface potential roll-up, drain-induced barrier lowering (DIBL), threshold voltage, and subthreshold swing (SS) as indexes of the SCE and analyzed their dependency on the channel thickness (number of atomic layers) and channel length. The minimum scalable channel length for a one-atomic-layer-thick MoS$_{2}$ MOSFET was determined from the threshold voltage roll-off to be 7.6,nm. The one-layer-thick device showed a small DIBL of 87,mV/V at a 20 nm gate length. By using high-k gate insulator, an SS lower than 70,mV/dec is achievable in sub-10-nm-scale devices.

According to the process scaling, radiation-hard devices are becoming sensitive to soft errors caused by Multiple Cell Upset (MCUs). In this paper, the parasitic bipolar effects are utilized to suppress MCUs of the radiation-hard dual-modular flip-flops. Device simulations reveal that a simultaneous flip of redundant latches is suppressed by storing opposite values instead of storing the same value due to its asymmetrical structure. The state of latches becomes a specific value after a particle hit due to the bipolar effects. Spallation neutron irradiation proves that MCUs are effectively suppressed in the D-FF arrays in which adjacent two latches in different FFs store opposite values. The redundant latch structure storing the opposite values is robust to the simultaneous flip.

A numerical model of multi-layered organic light emitting diode (OLED) is presented in this paper. The current density-voltage (J-V) model for OLED was performed by using the injection-limited current and bulk-limited current. The mobility equation was based on the field dependent model, so called “Poole-Frenkel mobility model.” The accuracy of this simulation was represented by comparing to the experimental results with a variable of EML thickness of multi-layered OLED device. There are two hetero-junction models which should be dealt with in the simulation. The Langevin recombination rate of electron and hole is also calculated through the device simulation.

In performing the program operation of the NAND-type flash memory array, the program-inhibited cell is applied by a positive voltage at the gate, i.e., word-line (WL) on the floating channel while the program cell is applied by program voltage as the two ends, drain select line (DSL) and source select line (SSL), are turned on with grounded bit-line (BL). In this manner, the self-boosting of silicon channel to avoid unwanted program operation is made possible. As the flash memory device is aggressively scaled down and the channel doping concentration is increased accordingly, the coupling phenomena among WL, floating gate (FG)/storage node, and silicon channel, which are crucial factors in the self-boosting scheme, should be investigated more thoroughly. In this work, the dependences of self-boosting of channel potential on channel length and doping concentration in the 2-D conventional planar and 3-D FinFET NAND-type flash memory devices based on bulk-silicon are investigated by both 2-D and 3-D numerical device simulations. Since there hardly exists realistic ways of measuring the channel potential by physical probing, the series of simulation works are believed to offer practical insights in the variation of channel potential inside a flash memory device.

A two-dimensional (2-D) physical model of n-channel poly-Si LDD TFTs in comparison with that of SD TFTs is presented to analyze hot-carrier degradation. The model is based on 2-D device simulator's Gaussian doping profiles for the source and drain junctions fitted to the lateral and vertical impurity profiles in poly-Si obtained from a 2-D process simulator. We have shown that, in the current saturation bias (Vg

We have developed a new simulation methodology for predicting shot noise intensity in Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). In our approach, shot noise in MOSFETs is calculated by employing a two dimensional device simulator in conjunction with the shot noise model of a p-n junction. The accuracy of the noise model has been demonstrated by comparing simulation results with measured noise data of p-n diodes. The intensity of shot noise in various n-MOSFET devices under various bias conditions was estimated beyond GHz operational frequency by using our simulation scheme. At DC or low-frequency region, sub-threshold current dominates the intensity of shot noise. Therefore, shot noise is independent on frequency in this region, and its intensity is exponentially depends on VG, proportional to L-1, and almost independent on VD. At high-frequency region above GHz frequency, on the other hand, shot noise intensity depends on frequency and is much larger than that of low-frequency region. In particular, the intensity of the RF shot noise is almost independent on L, VD and VG. This suggests that high-frequency shot noise intensity of MOSFETs is decided only by the conditions of source-bulk junction.

Practical design of double-gate undoped-channel FinFET has been investigated through 3D device simulations considering gate-induced drain leakage (GIDL). Optimization of FinFET structure including source/drain (S/D) profile was carried out for hp45 low standby power (LSTP) device whose gate length (Lg) is equal to 25 nm. GIDL is reduced by using gradual and offset S/D profile while degradation of drive current is minimized. Through the optimization of lateral straggle and offset of S/D profile, the ITRS specifications for drive current and off-state leakage current are achievable by FinFET with 10 nm fin width.

A well-defined test structure of organic static-induction transistor (SIT) having regularly sized nano-apertures in the gate electrode has been fabricated by colloidal lithography using 130-nm-diameter polystyrene spheres as shadow masks during vacuum deposition. Transistor characteristics of individual nano-apertures, namely 'nano-SIT,' have been measured using a conductive atomic-force-microscope (AFM) probe as a movable source electrode. Position of the source electrode is found to be more important to increase current on/off ratio than the distance between source and gate electrodes. Experimentally obtained maximum on/off ratio was 710 (at VDS = -4 V, VGS = 0 and 2 V) when a source electrode was fixed at the edge of gate aperture. The characteristics have been then analyzed using semiconductor device simulation by employing a strongly non-linear carrier mobility model in the CuPc layer. From device simulation, source current is found to be modulated not only by a saddle point potential in the gate aperture area but also by a pinch-off effect near the source electrode. According to the obtained results, a modified structure of organic SIT and an adequate acceptor concentration is proposed. On/off ratio of the modified organic SIT is expected to be 100 times larger than that of a conventional one.

We analyzed passivation film and the AlGaN surface states using open-gated structures of AlGaN/GaN HFETs by numerical simulation and experiments. From the analyses, we confirmed that insulating film conductivity plays the prominent roles in device performances of the wide bandgap semiconductor device. Device simulation confirmed that the difference in ID-VG characteristics is due to the trapping type of the surface states; electron-trap type or hole-trap type. For electron-trap type surface states, the surface potential pinned at electron quasi-Fermi level, which is the same as the channel potential in the open-gated FETs. As a result, surface potential of ungated region is equal to the channel electric potential resulting in the uncontrollability of the channel current by the edge placed gate electrode. For hole-trap type surface states, the surface potential is pinned at hole quasi-Fermi level, which must be the same as the edge placed gate electrode potential. Then, the AlGaN surface potential varies with the electrode potential variation allowing the control of channel current as if the whole channel is covered with a metal electrode. Experiments for open-gated FET with unpassivated surface show no current variation. This corresponds to electron-trap type surface states from the simulation. On the other hand, SiOX evaporated open-gated FET show current control by the gate electrode. The ID-VG characteristics resembles in simulated ID-VG characteristics with hole-trap surface states. However, the estimated time constants for the trap reactions are incredibly long due to the deep energy level for the surface states in wide bandgap semiconductors. In addition, the open-gated FET showed reverse threshold shift to the value expected from the hole-trap pinning levels. So, we concluded that the no current variation for the unpassivated open-gated FET can be attributed to electron traps in the surface states, but the control of the drain current for SiOX deposited open-gated FET is not by surface hole-traps, but by slightly conductive passivation film of SiOX.

In this paper we apply a parallel adaptive solution algorithm to simulate nanoscale double-gate metal-oxide-semiconductor field effect transistors (MOSFETs) on a personal computer (PC)-based Linux cluster with the message passing interface (MPI) libraries. Based on a posteriori error estimation, the triangular mesh generation, the adaptive finite volume method, the monotone iterative method, and the parallel domain decomposition algorithm, a set of two-dimensional quantum correction hydrodynamic (HD) equations is solved numerically on our constructed cluster system. This parallel adaptive simulation methodology with 1-irregular mesh was successfully developed and applied to deep-submicron semiconductor device simulation in our recent work. A 10 nm n-type double-gate MOSFET is simulated with the developed parallel adaptive simulator. In terms of physical quantities and refined adaptive mesh, simulation results demonstrate very good accuracy and computational efficiency. Benchmark results, such as load-balancing, speedup, and parallel efficiency are achieved and exhibit excellent parallel performance. On a 16 nodes PC-based Linux cluster, the maximum difference among CPUs is less than 6%. A 12.8 times speedup and 80% parallel efficiency are simultaneously attained with respect to different simulation cases.

TCAD is gaining acceptance in the heterostructure industry. This article discusses the specific challenges a device simulator must manage to be a useful tool in designing and optimizing modern heterostructure devices. Example simulation results are given for HEMTs and HBTs, illustrating the complex physical processes in heterostructure devices, such as nonlocal effects in carrier transport, lattice self-heating, hot-electron effects, traps, electron tunneling, and quantum transport.

DC and RF performances of AlGaN/GaN HEMTs are simulated using a two-dimensional device simulator with the material parameters of GaN and AlGaN. The cut-off frequency is estimated as 205 GHz at the gate length of 0.05 µm and the drain breakdown voltage at this gate length is over 10 V. The values are satisfactory for millimeter wavelength power applications. The use of thin AlGaN layers has key importance to alleviate gate parasitic capacitance effects at this gate length.

A TCAD implementation of a quantum-mechanical mobility model in the commercial device simulator DESSIS_ISE is presented. The model makes use of an integrated 1D Schrodinger-Poisson solver. Effective mobilities µeff and transfer characteristics are calculated for DGSOI MOSFETs with a wide range of silicon film thickness tSi and buried-oxide thickness tbox. It is shown that the volume-inversion related enhancement of µeff for tSi 10 nm is bound to symmetrical DGSOIs, whereas SIMOX based devices with thick buried oxides limit µeff to the bulk value. The still immature technology makes a conclusive comparison with experimental data impossible.

A realistic 3-D process/device simulation method was developed for investigating the fluctuation in device characteristics induced by the statistical nature of the number and position of discrete dopant atoms. Monte Carlo procedures are applied for both ion implantation and dopant diffusion/activation simulations. Atomistic potential profile for device simulation is calculated from discrete dopant atom positions by incorporating the long-range part of Coulomb potential. This simulation was used to investigate the variations in characteristics of sub-100 nm CMOS devices induced by realistic dopant fluctuations considering practical device fabrication processes. In particular, sensitivity analysis of the threshold voltage fluctuation was performed in terms of the independent dopant contribution, such as that of the dopant in the source/drain or channel region.

RF noise in quarter-micron nMOSFETs is analysed on the device level based on Shockley's impedance field method. The impact of different transport models and physical parameters is discussed in detail. Well-calibrated drift-diffusion and energy-balance models give very similar results for noise current spectral densities and noise figures. We show by numerical simulations with the general-purpose device simulator DESSIS_ISE that the hot-electron effect on RF noise is unimportant under normal operating conditions and that thermal substrate noise is dominant below 0.5 GHz. The contribution of energy-current fluctuations to the terminal noise is found to be negligible. Application of noise sources generated in bulk full-band Monte Carlo simulations changes the noise figures considerably, which underlines the importance of proper noise source models for far-from-equilibrium conditions.

Impact ionization and thermionic tunnelling as two possible breakdown mechanisms in scaled pseudomorphic high electron mobility transistors (PHEMTs) are investigated by Monte Carlo (MC) device simulations. Impact ionization is included in MC simulation as an additional scattering mechanism whereas thermionic tunnelling is treated in the WKB approximation during each time step in self-consistent MC simulation. Thermionic tunnelling starts at very low drain voltages but then quickly saturates. Therefore, it should not drastically affect the performance of scaled devices. Impact ionization threshold occurs at greater drain voltages which should assure a reasonable operation voltage scale for all scaled PHEMTs.

The density gradient (DG) model is tested for its ability to describe tunneling currents through thin insulating barriers. Simulations of single barriers (MOS diodes, MOSFETs) and double barriers (RTDs) show the limitations of the DG model. For comparison, direct tunneling currents are calculated with the Schrodinger-Bardeen method and used as benchmark. The negative differential resistance (NDR) observed in simulating tunneling currents with the DG model turns out to be an artifact related to large density differences in the semiconductor regions. Such spurious NDR occurs both for single and double barriers and vanishes, if all semiconductor regions are equally doped.

A three-dimensional mesh generation method in which triangulation of the domain boundary is performed first is desirable since such a method would make it easier to achieve the requirements for the mesh around the boundary. We have developed a mesh generator for a 3D device simulator based on this approach. This mesh generator recursively subdivides a box that includes the whole domain into smaller boxes (cells), a method known as the octree technique. Although our mesh generator is similar to previously reported mesh generators in the sense that it utilizes recursive subdivision of elements, its major difference is that it constructs a triangular mesh upon boundaries of the domain first and this triangular mesh is not changed in the following processes. In order to generate a mesh suitable for the control volume method, a "forbidden region" is introduced and mesh points in the domain are allocated outside of this region. Since the triangular mesh is determined prior to tessellation of the domain, this method is suitable for handling layered mesh along the boundary, which is often necessary to estimate large flows parallel to the boundary precisely. A simple method to provide a layered mesh for a planar boundary is incorporated into the mesh generator. This mesh generator is integrated within our in-house three-dimensional device simulation system. The simulator's practicality is demonstrated through analysis of the reverse narrow channel effect for MOSFETs with LOCOS isolation structures. The effect of protection of the boundary by the layered mesh is also examined by calculating Id-Vg characteristics of a MOSFET with an oblique Si surface, and it is shown that protection of the whole surface of the channel region is necessary to estimate drain current correctly.