Silicon Nitride Passivated Ultra Low Noise InAlAs/InGaAs HEMT's with n<SUP>+</SUP>-InGaAs/n<SUP>+</SUP>-InAlAs Cap Layer

Yohtaro UMEDA; Takatomo ENOKI; Kunihiro ARAI; Yasunobu ISHII

Silicon Nitride Passivated Ultra Low Noise InAlAs/InGaAs HEMT's with n⁺-InGaAs/n⁺-InAlAs Cap Layer

Yohtaro UMEDA, Takatomo ENOKI, Kunihiro ARAI, Yasunobu ISHII

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Noise characteristics of InAlAs/InGaAs HEMT's passivated by SiN are investigated to ascertain their suitability for practical applications in circuit such as MMIC's. A 0.18-µm-gate-length device with 125-µm-gate width and 8-gate fingers showed the lowest minimum noise figure of 0.43 dB at 26 GHz with an associated gain of 8.5 dB of any passivated device ever reported. This value is also comparable to the lowest reported minimum noise figure obtained by bare InAlAs/InGaAs HEMT's in spite of increased parasitic capacitances due to the SiN passivation. Thes excellent noise performance was achieved by employing non-alloyed ohmic contact, a T-shaped gate geometry and a multi-finger gate pattern. To reduce the contact resistance of the non-alloyed ohmic contact, a novel n⁺-InGaAs/n⁺-InAlAs cap layer was used resulting in a very low contact resistance of 0.09 Ωmm and a low sheet resistance for all layers of 145 Ω/sq. No increase in these resistances was observed after SiN passivation, and a very low source resistance of 0.16 Ωmm was obtained. An analysis of equivalent circuit parameters revealed that the T-shaped gate and multi-finger gate pattern drastically decrease gate resistance.

Publication: IEICE TRANSACTIONS on Electronics Vol.E75-C No.6 pp.649-655

Publication Date: 1992/06/25

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Type of Manuscript: Special Section PAPER (Special Issue on MMIC Technology)

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Yohtaro UMEDA, Takatomo ENOKI, Kunihiro ARAI, Yasunobu ISHII, "Silicon Nitride Passivated Ultra Low Noise InAlAs/InGaAs HEMT's with n+-InGaAs/n+-InAlAs Cap Layer" in IEICE TRANSACTIONS on Electronics, vol. E75-C, no. 6, pp. 649-655, June 1992, doi: .
Abstract: Noise characteristics of InAlAs/InGaAs HEMT's passivated by SiN are investigated to ascertain their suitability for practical applications in circuit such as MMIC's. A 0.18-µm-gate-length device with 125-µm-gate width and 8-gate fingers showed the lowest minimum noise figure of 0.43 dB at 26 GHz with an associated gain of 8.5 dB of any passivated device ever reported. This value is also comparable to the lowest reported minimum noise figure obtained by bare InAlAs/InGaAs HEMT's in spite of increased parasitic capacitances due to the SiN passivation. Thes excellent noise performance was achieved by employing non-alloyed ohmic contact, a T-shaped gate geometry and a multi-finger gate pattern. To reduce the contact resistance of the non-alloyed ohmic contact, a novel n⁺-InGaAs/n⁺-InAlAs cap layer was used resulting in a very low contact resistance of 0.09 Ωmm and a low sheet resistance for all layers of 145 Ω/sq. No increase in these resistances was observed after SiN passivation, and a very low source resistance of 0.16 Ωmm was obtained. An analysis of equivalent circuit parameters revealed that the T-shaped gate and multi-finger gate pattern drastically decrease gate resistance.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e75-c_6_649/_p

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@ARTICLE{e75-c_6_649,
author={Yohtaro UMEDA, Takatomo ENOKI, Kunihiro ARAI, Yasunobu ISHII, },
journal={IEICE TRANSACTIONS on Electronics},
title={Silicon Nitride Passivated Ultra Low Noise InAlAs/InGaAs HEMT's with n+-InGaAs/n+-InAlAs Cap Layer},
year={1992},
volume={E75-C},
number={6},
pages={649-655},
abstract={Noise characteristics of InAlAs/InGaAs HEMT's passivated by SiN are investigated to ascertain their suitability for practical applications in circuit such as MMIC's. A 0.18-µm-gate-length device with 125-µm-gate width and 8-gate fingers showed the lowest minimum noise figure of 0.43 dB at 26 GHz with an associated gain of 8.5 dB of any passivated device ever reported. This value is also comparable to the lowest reported minimum noise figure obtained by bare InAlAs/InGaAs HEMT's in spite of increased parasitic capacitances due to the SiN passivation. Thes excellent noise performance was achieved by employing non-alloyed ohmic contact, a T-shaped gate geometry and a multi-finger gate pattern. To reduce the contact resistance of the non-alloyed ohmic contact, a novel n⁺-InGaAs/n⁺-InAlAs cap layer was used resulting in a very low contact resistance of 0.09 Ωmm and a low sheet resistance for all layers of 145 Ω/sq. No increase in these resistances was observed after SiN passivation, and a very low source resistance of 0.16 Ωmm was obtained. An analysis of equivalent circuit parameters revealed that the T-shaped gate and multi-finger gate pattern drastically decrease gate resistance.},
keywords={},
doi={},
ISSN={},
month={June},}

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TY - JOUR
TI - Silicon Nitride Passivated Ultra Low Noise InAlAs/InGaAs HEMT's with n+-InGaAs/n+-InAlAs Cap Layer
T2 - IEICE TRANSACTIONS on Electronics
SP - 649
EP - 655
AU - Yohtaro UMEDA
AU - Takatomo ENOKI
AU - Kunihiro ARAI
AU - Yasunobu ISHII
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E75-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1992
AB - Noise characteristics of InAlAs/InGaAs HEMT's passivated by SiN are investigated to ascertain their suitability for practical applications in circuit such as MMIC's. A 0.18-µm-gate-length device with 125-µm-gate width and 8-gate fingers showed the lowest minimum noise figure of 0.43 dB at 26 GHz with an associated gain of 8.5 dB of any passivated device ever reported. This value is also comparable to the lowest reported minimum noise figure obtained by bare InAlAs/InGaAs HEMT's in spite of increased parasitic capacitances due to the SiN passivation. Thes excellent noise performance was achieved by employing non-alloyed ohmic contact, a T-shaped gate geometry and a multi-finger gate pattern. To reduce the contact resistance of the non-alloyed ohmic contact, a novel n⁺-InGaAs/n⁺-InAlAs cap layer was used resulting in a very low contact resistance of 0.09 Ωmm and a low sheet resistance for all layers of 145 Ω/sq. No increase in these resistances was observed after SiN passivation, and a very low source resistance of 0.16 Ωmm was obtained. An analysis of equivalent circuit parameters revealed that the T-shaped gate and multi-finger gate pattern drastically decrease gate resistance.
ER -