Noise Reduction Techniques for a 64-kb ECL-CMOS SRAM with a 2-ns Cycle Time

Kenichi OHHATA; Yoshiaki SAKURAI; Hiroaki NAMBU; Kazuo KANETANI; Youji IDEI; Toshirou HIRAMOTO; Nobuo TAMBA; Kunihiko YAMAGUCHI; Masanori ODAKA; Kunihiko WATANABE; Takahide IKEDA; Noriyuki HOMMA

Noise Reduction Techniques for a 64-kb ECL-CMOS SRAM with a 2-ns Cycle Time

Kenichi OHHATA, Yoshiaki SAKURAI, Hiroaki NAMBU, Kazuo KANETANI, Youji IDEI, Toshirou HIRAMOTO, Nobuo TAMBA, Kunihiko YAMAGUCHI, Masanori ODAKA, Kunihiko WATANABE, Takahide IKEDA, Noriyuki HOMMA

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An ECL-CMOS SRAM technology is proposed which features a combination of ECL word drivers, ECL write circuits and low-voltage CMOS cells. This technology assures both ultra-high-speed and high-density. In the ECL-CMOS SRAM,various kinds of noise generated during the write cycle seriously affect the memory performance, because it has much faster access than conventional SRAMs. To overcome this problem, we propose three noise reduction techniques; a noise reduction clamp circuit, an emitter follower with damping capacitor and a twisted bit line structure with "normally on" equalizer. These techniques allow fast accese and cycle times. To evaluate these techniques, a 64-kb SRAM chip was fabricated using 0.5-µm BiCMOS technology. This SRAM has a short cycle time of 2 ns and a very fast access time of 1.5 ns. Evaluation proves the usefulness of these techniques.

Publication: IEICE TRANSACTIONS on Electronics Vol.E76-C No.11 pp.1611-1619

Publication Date: 1993/11/25

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Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories)

Category: SRAM

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Kenichi OHHATA, Yoshiaki SAKURAI, Hiroaki NAMBU, Kazuo KANETANI, Youji IDEI, Toshirou HIRAMOTO, Nobuo TAMBA, Kunihiko YAMAGUCHI, Masanori ODAKA, Kunihiko WATANABE, Takahide IKEDA, Noriyuki HOMMA, "Noise Reduction Techniques for a 64-kb ECL-CMOS SRAM with a 2-ns Cycle Time" in IEICE TRANSACTIONS on Electronics, vol. E76-C, no. 11, pp. 1611-1619, November 1993, doi: .
Abstract: An ECL-CMOS SRAM technology is proposed which features a combination of ECL word drivers, ECL write circuits and low-voltage CMOS cells. This technology assures both ultra-high-speed and high-density. In the ECL-CMOS SRAM,various kinds of noise generated during the write cycle seriously affect the memory performance, because it has much faster access than conventional SRAMs. To overcome this problem, we propose three noise reduction techniques; a noise reduction clamp circuit, an emitter follower with damping capacitor and a twisted bit line structure with "normally on" equalizer. These techniques allow fast accese and cycle times. To evaluate these techniques, a 64-kb SRAM chip was fabricated using 0.5-µm BiCMOS technology. This SRAM has a short cycle time of 2 ns and a very fast access time of 1.5 ns. Evaluation proves the usefulness of these techniques.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e76-c_11_1611/_p

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@ARTICLE{e76-c_11_1611,
author={Kenichi OHHATA, Yoshiaki SAKURAI, Hiroaki NAMBU, Kazuo KANETANI, Youji IDEI, Toshirou HIRAMOTO, Nobuo TAMBA, Kunihiko YAMAGUCHI, Masanori ODAKA, Kunihiko WATANABE, Takahide IKEDA, Noriyuki HOMMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Noise Reduction Techniques for a 64-kb ECL-CMOS SRAM with a 2-ns Cycle Time},
year={1993},
volume={E76-C},
number={11},
pages={1611-1619},
abstract={An ECL-CMOS SRAM technology is proposed which features a combination of ECL word drivers, ECL write circuits and low-voltage CMOS cells. This technology assures both ultra-high-speed and high-density. In the ECL-CMOS SRAM,various kinds of noise generated during the write cycle seriously affect the memory performance, because it has much faster access than conventional SRAMs. To overcome this problem, we propose three noise reduction techniques; a noise reduction clamp circuit, an emitter follower with damping capacitor and a twisted bit line structure with "normally on" equalizer. These techniques allow fast accese and cycle times. To evaluate these techniques, a 64-kb SRAM chip was fabricated using 0.5-µm BiCMOS technology. This SRAM has a short cycle time of 2 ns and a very fast access time of 1.5 ns. Evaluation proves the usefulness of these techniques.},
keywords={},
doi={},
ISSN={},
month={November},}

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TY - JOUR
TI - Noise Reduction Techniques for a 64-kb ECL-CMOS SRAM with a 2-ns Cycle Time
T2 - IEICE TRANSACTIONS on Electronics
SP - 1611
EP - 1619
AU - Kenichi OHHATA
AU - Yoshiaki SAKURAI
AU - Hiroaki NAMBU
AU - Kazuo KANETANI
AU - Youji IDEI
AU - Toshirou HIRAMOTO
AU - Nobuo TAMBA
AU - Kunihiko YAMAGUCHI
AU - Masanori ODAKA
AU - Kunihiko WATANABE
AU - Takahide IKEDA
AU - Noriyuki HOMMA
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E76-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 1993
AB - An ECL-CMOS SRAM technology is proposed which features a combination of ECL word drivers, ECL write circuits and low-voltage CMOS cells. This technology assures both ultra-high-speed and high-density. In the ECL-CMOS SRAM,various kinds of noise generated during the write cycle seriously affect the memory performance, because it has much faster access than conventional SRAMs. To overcome this problem, we propose three noise reduction techniques; a noise reduction clamp circuit, an emitter follower with damping capacitor and a twisted bit line structure with "normally on" equalizer. These techniques allow fast accese and cycle times. To evaluate these techniques, a 64-kb SRAM chip was fabricated using 0.5-µm BiCMOS technology. This SRAM has a short cycle time of 2 ns and a very fast access time of 1.5 ns. Evaluation proves the usefulness of these techniques.
ER -