A Novel CMOS Structure with Polysilicon Source/Drain (PSD) Transistors by Self-Aligned Silicidation

Masahiro SHIMIZU; Takehisa YAMAGUCHI; Masahide INUISHI; Katsuhiro TSUKAMOTO

A Novel CMOS Structure with Polysilicon Source/Drain (PSD) Transistors by Self-Aligned Silicidation

Masahiro SHIMIZU, Takehisa YAMAGUCHI, Masahide INUISHI, Katsuhiro TSUKAMOTO

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A novel CMOS structure has been developed using Ti-salicide PSD transistor formed by a new self-aligned method. Both N-channel and P-channel PSD transistors exhibit excellent short-channel behaviors down to the sub-half-micrometer region with shallow S/D junctions formed by dopant diffusion from polysilicons. New salicide process has been developed for the PSD structure and can effectively reduce the sheet resistances of the S/D polysilicon and the polysilicon gate to as low as 45Ω/. As a result, the low resistive local interconnects can be successfully implemented by the Ti-salicide S/D polysilicon merged with contacts by self-alignment. More-over it is found that shallow Ti-salicide S/D junctions with the PSD structure can achieve approximately 12 orders of magnitude lower area leakage current than that of the conventional implanted S/D junctions by eliminating implanted damage and preventing penetration of silicide into junctions with the elevated structure of S/D polysilicon layer. Furthermore CMOS ring oscillators having PSD transistors with an effective channel length of 0.4 µm were fabricated using the salicided S/D polysilicon as a local interconnect between the N⁺ and the P⁺ regions, and successfully operated with a propagation delay time of 50 ps/stage at a supply voltage of 5 V.

Publication: IEICE TRANSACTIONS on Electronics Vol.E76-C No.4 pp.532-540

Publication Date: 1993/04/25

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Type of Manuscript: Special Section PAPER (Special Issue on Sub-Half Micron Si Device and Process Technologies)

Category: Device Technology

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Masahiro SHIMIZU, Takehisa YAMAGUCHI, Masahide INUISHI, Katsuhiro TSUKAMOTO, "A Novel CMOS Structure with Polysilicon Source/Drain (PSD) Transistors by Self-Aligned Silicidation" in IEICE TRANSACTIONS on Electronics, vol. E76-C, no. 4, pp. 532-540, April 1993, doi: .
Abstract: A novel CMOS structure has been developed using Ti-salicide PSD transistor formed by a new self-aligned method. Both N-channel and P-channel PSD transistors exhibit excellent short-channel behaviors down to the sub-half-micrometer region with shallow S/D junctions formed by dopant diffusion from polysilicons. New salicide process has been developed for the PSD structure and can effectively reduce the sheet resistances of the S/D polysilicon and the polysilicon gate to as low as 45Ω/. As a result, the low resistive local interconnects can be successfully implemented by the Ti-salicide S/D polysilicon merged with contacts by self-alignment. More-over it is found that shallow Ti-salicide S/D junctions with the PSD structure can achieve approximately 12 orders of magnitude lower area leakage current than that of the conventional implanted S/D junctions by eliminating implanted damage and preventing penetration of silicide into junctions with the elevated structure of S/D polysilicon layer. Furthermore CMOS ring oscillators having PSD transistors with an effective channel length of 0.4 µm were fabricated using the salicided S/D polysilicon as a local interconnect between the N⁺ and the P⁺ regions, and successfully operated with a propagation delay time of 50 ps/stage at a supply voltage of 5 V.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e76-c_4_532/_p

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@ARTICLE{e76-c_4_532,
author={Masahiro SHIMIZU, Takehisa YAMAGUCHI, Masahide INUISHI, Katsuhiro TSUKAMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Novel CMOS Structure with Polysilicon Source/Drain (PSD) Transistors by Self-Aligned Silicidation},
year={1993},
volume={E76-C},
number={4},
pages={532-540},
abstract={A novel CMOS structure has been developed using Ti-salicide PSD transistor formed by a new self-aligned method. Both N-channel and P-channel PSD transistors exhibit excellent short-channel behaviors down to the sub-half-micrometer region with shallow S/D junctions formed by dopant diffusion from polysilicons. New salicide process has been developed for the PSD structure and can effectively reduce the sheet resistances of the S/D polysilicon and the polysilicon gate to as low as 45Ω/. As a result, the low resistive local interconnects can be successfully implemented by the Ti-salicide S/D polysilicon merged with contacts by self-alignment. More-over it is found that shallow Ti-salicide S/D junctions with the PSD structure can achieve approximately 12 orders of magnitude lower area leakage current than that of the conventional implanted S/D junctions by eliminating implanted damage and preventing penetration of silicide into junctions with the elevated structure of S/D polysilicon layer. Furthermore CMOS ring oscillators having PSD transistors with an effective channel length of 0.4 µm were fabricated using the salicided S/D polysilicon as a local interconnect between the N⁺ and the P⁺ regions, and successfully operated with a propagation delay time of 50 ps/stage at a supply voltage of 5 V.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - A Novel CMOS Structure with Polysilicon Source/Drain (PSD) Transistors by Self-Aligned Silicidation
T2 - IEICE TRANSACTIONS on Electronics
SP - 532
EP - 540
AU - Masahiro SHIMIZU
AU - Takehisa YAMAGUCHI
AU - Masahide INUISHI
AU - Katsuhiro TSUKAMOTO
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E76-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1993
AB - A novel CMOS structure has been developed using Ti-salicide PSD transistor formed by a new self-aligned method. Both N-channel and P-channel PSD transistors exhibit excellent short-channel behaviors down to the sub-half-micrometer region with shallow S/D junctions formed by dopant diffusion from polysilicons. New salicide process has been developed for the PSD structure and can effectively reduce the sheet resistances of the S/D polysilicon and the polysilicon gate to as low as 45Ω/. As a result, the low resistive local interconnects can be successfully implemented by the Ti-salicide S/D polysilicon merged with contacts by self-alignment. More-over it is found that shallow Ti-salicide S/D junctions with the PSD structure can achieve approximately 12 orders of magnitude lower area leakage current than that of the conventional implanted S/D junctions by eliminating implanted damage and preventing penetration of silicide into junctions with the elevated structure of S/D polysilicon layer. Furthermore CMOS ring oscillators having PSD transistors with an effective channel length of 0.4 µm were fabricated using the salicided S/D polysilicon as a local interconnect between the N⁺ and the P⁺ regions, and successfully operated with a propagation delay time of 50 ps/stage at a supply voltage of 5 V.
ER -