A novel isolation structure which has a buried insulator between polysilicon electrodes (BIPS) has been developed. The BIPS isolation employs the refilling CVD-oxides in openings between polysilicon electrodes by photoresist etchback process. Device characteristics and parasitic effects of BIPS isolation have been compared with that of LOCOS isolation. Using BIPS isolation, we can almost suppress the narrow-channel effects and achieve the deep submicron isolation. No degradation on the subthreshold decay of devices with BIPS isolation can be obtained. The use of BIPS isolation technology yields a DRAM cell of small area. The successful fabrication of deep submicron devices with BIPS isolation clearly demonstrates that this technology has superior ability to overcome the LOCOS isolation.

A novel CMOS structure has been developed using Ti-salicide PSD transistor formed by a new self-aligned method. Both N-channel and P-channel PSD transistors exhibit excellent short-channel behaviors down to the sub-half-micrometer region with shallow S/D junctions formed by dopant diffusion from polysilicons. New salicide process has been developed for the PSD structure and can effectively reduce the sheet resistances of the S/D polysilicon and the polysilicon gate to as low as 45Ω/. As a result, the low resistive local interconnects can be successfully implemented by the Ti-salicide S/D polysilicon merged with contacts by self-alignment. More-over it is found that shallow Ti-salicide S/D junctions with the PSD structure can achieve approximately 12 orders of magnitude lower area leakage current than that of the conventional implanted S/D junctions by eliminating implanted damage and preventing penetration of silicide into junctions with the elevated structure of S/D polysilicon layer. Furthermore CMOS ring oscillators having PSD transistors with an effective channel length of 0.4 µm were fabricated using the salicided S/D polysilicon as a local interconnect between the N+ and the P+ regions, and successfully operated with a propagation delay time of 50 ps/stage at a supply voltage of 5 V.

Hot-carrier characteristics in ultra-thin SOI MOSFET's (T-SOI MOSFET's) with gate-overlapped LDD have been investigated. The change in transistor static characteristics after hot carrier stress was mainly observed as positive threshold voltage (Vt) shifts due to trapped electrons, while in bulk-Si MOSFET's drain current degradation was dominant. The hot-carrier life time in T-SOI MOSFET's was comparable to that in bulk-Si devices at low drain voltage, but the life time dependence on drain voltage was different from that in bulk-Si MOSFET's, and the Vt degraded rapidly at the condition that parasitic bipolar breakdown began to occur. This implies that the drain supply voltage in T-SOI MOSFET's is determined directly by parasitic bipolar breakdown voltage unlike bulk-Si MOSFET's in which it is determined by hot-carrier reliability. The gate-overlapped LDD structure was compared with single drain structure and proved to provide better hot-carrier endurance by the improvement of the parasitic bipolar breakdown voltage. The hot-carrier reliability in the back channels of T-SOI MOSFET's was also investigated, and it was found that the back channel tends to be degraded more easily than front channel with large positive Vt shifts. These results suggest that the front Vt shifts in T-SOI devices are related with electron injection into the back surface of the T-SOI layer through charge coupling at the condition that the parasitic bipolar breakdown occurs.

A 4-Gb AG-AND flash memory was fabricated by using a 90-nm CMOS technology. To reduce cell size, an inversion-layer-bit-line technology was developed, enabling the elimination of both shallow trench isolations and diffusion layers from the memory cells. The inversion-layer-bit-line technology combined with a multilevel cell technique achieved a bit area 2F2 of 0.0162 µm2, resulting in a chip size of 126 mm2. Both an address and temperature compensation techniques control the resistance of the inversion-layer local bit line. Source-side hot-electron injection programming with self-boosted charge, accumulated in inversion-layer bit lines under assist gates, reduces the dispersal of programming characteristics and also reduces the time overhead of pre-charging the bit lines. This self-boosted charge-injection scheme achieves a programming throughput of 10 MB/s.