Development of Improved Low Power MUSE (HDTV) Decoder Chip Set 2.5th Generation MUSE Chip Set

Kiyoshi KOHIYAMA; Kota OTSUBO; Hidenaga TAKAHASHI; Kiyotaka OGAWA; Yukio OTOBE

Development of Improved Low Power MUSE (HDTV) Decoder Chip Set 2.5th Generation MUSE Chip Set

Kiyoshi KOHIYAMA, Kota OTSUBO, Hidenaga TAKAHASHI, Kiyotaka OGAWA, Yukio OTOBE

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Development of low power MUSE (Multiple Sub-Nyquist Sampling Encoding) chip set through reduction in operating voltage (from 5 V to 3.7 V) is described. This leads to great cost reduction since the chips could be mounted on low cost plastic packages and the necessity for cooling fans to dissipate heat was obviated. To maintain compatibility with standard 5 V analog and digital peripherals such as 4 Mbit DRAMs and an A/D converter, a special voltage-level converter was also developed.

Publication: IEICE TRANSACTIONS on Electronics Vol.E77-C No.12 pp.1859-1864

Publication Date: 1994/12/25

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Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)

Category: Multimedia System LSIs

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Kiyoshi KOHIYAMA, Kota OTSUBO, Hidenaga TAKAHASHI, Kiyotaka OGAWA, Yukio OTOBE, "Development of Improved Low Power MUSE (HDTV) Decoder Chip Set 2.5th Generation MUSE Chip Set" in IEICE TRANSACTIONS on Electronics, vol. E77-C, no. 12, pp. 1859-1864, December 1994, doi: .
Abstract: Development of low power MUSE (Multiple Sub-Nyquist Sampling Encoding) chip set through reduction in operating voltage (from 5 V to 3.7 V) is described. This leads to great cost reduction since the chips could be mounted on low cost plastic packages and the necessity for cooling fans to dissipate heat was obviated. To maintain compatibility with standard 5 V analog and digital peripherals such as 4 Mbit DRAMs and an A/D converter, a special voltage-level converter was also developed.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e77-c_12_1859/_p

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@ARTICLE{e77-c_12_1859,
author={Kiyoshi KOHIYAMA, Kota OTSUBO, Hidenaga TAKAHASHI, Kiyotaka OGAWA, Yukio OTOBE, },
journal={IEICE TRANSACTIONS on Electronics},
title={Development of Improved Low Power MUSE (HDTV) Decoder Chip Set 2.5th Generation MUSE Chip Set},
year={1994},
volume={E77-C},
number={12},
pages={1859-1864},
abstract={Development of low power MUSE (Multiple Sub-Nyquist Sampling Encoding) chip set through reduction in operating voltage (from 5 V to 3.7 V) is described. This leads to great cost reduction since the chips could be mounted on low cost plastic packages and the necessity for cooling fans to dissipate heat was obviated. To maintain compatibility with standard 5 V analog and digital peripherals such as 4 Mbit DRAMs and an A/D converter, a special voltage-level converter was also developed.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - Development of Improved Low Power MUSE (HDTV) Decoder Chip Set 2.5th Generation MUSE Chip Set
T2 - IEICE TRANSACTIONS on Electronics
SP - 1859
EP - 1864
AU - Kiyoshi KOHIYAMA
AU - Kota OTSUBO
AU - Hidenaga TAKAHASHI
AU - Kiyotaka OGAWA
AU - Yukio OTOBE
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 1994
AB - Development of low power MUSE (Multiple Sub-Nyquist Sampling Encoding) chip set through reduction in operating voltage (from 5 V to 3.7 V) is described. This leads to great cost reduction since the chips could be mounted on low cost plastic packages and the necessity for cooling fans to dissipate heat was obviated. To maintain compatibility with standard 5 V analog and digital peripherals such as 4 Mbit DRAMs and an A/D converter, a special voltage-level converter was also developed.
ER -