An Efficient Self-Timed Queue Architecture for ATM Switch LSIs

Harufusa KONDOH; Hideaki YAMANAKA; Masahiko ISHIWAKI; Yoshio MATSUDA; Masao NAKAYA

An Efficient Self-Timed Queue Architecture for ATM Switch LSIs

Harufusa KONDOH, Hideaki YAMANAKA, Masahiko ISHIWAKI, Yoshio MATSUDA, Masao NAKAYA

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A new approach to implement queues for controlling ATM switch LSI is presented. In many conventional architecture, external FIFOs are provided for each output link and used to manage the address of the buffer in an ATM switch. We reduce the number of FIFOs by using a self-timed queue with a search circuit that finds the earliest entry for each output link. Using this architecture, number of the FIFOs is reduced to 1/N, where N is the switch size. Delay priority and multicasting can be supported without doubling the number of the queues. This new queue can also be utilized as an ATM switch by itself. Evaluation chip was fabricated using 0.5-µm CMOS process technology. Inter-stage transfer speed over 500 MHz and cycle time over 125 MHz was obtained. This performance is enough for a 622-Mbps 1616 ATM Switch.

Publication: IEICE TRANSACTIONS on Electronics Vol.E77-C No.12 pp.1865-1872

Publication Date: 1994/12/25

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Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)

Category: Multimedia System LSIs

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Harufusa KONDOH, Hideaki YAMANAKA, Masahiko ISHIWAKI, Yoshio MATSUDA, Masao NAKAYA, "An Efficient Self-Timed Queue Architecture for ATM Switch LSIs" in IEICE TRANSACTIONS on Electronics, vol. E77-C, no. 12, pp. 1865-1872, December 1994, doi: .
Abstract: A new approach to implement queues for controlling ATM switch LSI is presented. In many conventional architecture, external FIFOs are provided for each output link and used to manage the address of the buffer in an ATM switch. We reduce the number of FIFOs by using a self-timed queue with a search circuit that finds the earliest entry for each output link. Using this architecture, number of the FIFOs is reduced to 1/N, where N is the switch size. Delay priority and multicasting can be supported without doubling the number of the queues. This new queue can also be utilized as an ATM switch by itself. Evaluation chip was fabricated using 0.5-µm CMOS process technology. Inter-stage transfer speed over 500 MHz and cycle time over 125 MHz was obtained. This performance is enough for a 622-Mbps 1616 ATM Switch.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e77-c_12_1865/_p

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@ARTICLE{e77-c_12_1865,
author={Harufusa KONDOH, Hideaki YAMANAKA, Masahiko ISHIWAKI, Yoshio MATSUDA, Masao NAKAYA, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Efficient Self-Timed Queue Architecture for ATM Switch LSIs},
year={1994},
volume={E77-C},
number={12},
pages={1865-1872},
abstract={A new approach to implement queues for controlling ATM switch LSI is presented. In many conventional architecture, external FIFOs are provided for each output link and used to manage the address of the buffer in an ATM switch. We reduce the number of FIFOs by using a self-timed queue with a search circuit that finds the earliest entry for each output link. Using this architecture, number of the FIFOs is reduced to 1/N, where N is the switch size. Delay priority and multicasting can be supported without doubling the number of the queues. This new queue can also be utilized as an ATM switch by itself. Evaluation chip was fabricated using 0.5-µm CMOS process technology. Inter-stage transfer speed over 500 MHz and cycle time over 125 MHz was obtained. This performance is enough for a 622-Mbps 1616 ATM Switch.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - An Efficient Self-Timed Queue Architecture for ATM Switch LSIs
T2 - IEICE TRANSACTIONS on Electronics
SP - 1865
EP - 1872
AU - Harufusa KONDOH
AU - Hideaki YAMANAKA
AU - Masahiko ISHIWAKI
AU - Yoshio MATSUDA
AU - Masao NAKAYA
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 1994
AB - A new approach to implement queues for controlling ATM switch LSI is presented. In many conventional architecture, external FIFOs are provided for each output link and used to manage the address of the buffer in an ATM switch. We reduce the number of FIFOs by using a self-timed queue with a search circuit that finds the earliest entry for each output link. Using this architecture, number of the FIFOs is reduced to 1/N, where N is the switch size. Delay priority and multicasting can be supported without doubling the number of the queues. This new queue can also be utilized as an ATM switch by itself. Evaluation chip was fabricated using 0.5-µm CMOS process technology. Inter-stage transfer speed over 500 MHz and cycle time over 125 MHz was obtained. This performance is enough for a 622-Mbps 1616 ATM Switch.
ER -