A Half-Pel Precision Motion Estimation Processor for NTSC-Resolution Video

Shin-ichi URAMOTO; Akihiko TAKABATAKE; Mitsuyoshi SUZUKI; Hiroki SAKURAI; Masahiko YOSHIMOTO

A Half-Pel Precision Motion Estimation Processor for NTSC-Resolution Video

Shin-ichi URAMOTO, Akihiko TAKABATAKE, Mitsuyoshi SUZUKI, Hiroki SAKURAI, Masahiko YOSHIMOTO

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The hybrid coding with motion compensated prediction and discrete cosine transform (MC+DCT) has been recognized as the standard technique in motion picture coding. In this paper, a motion estimation processor compatible with ITU-T H.261 and MPEG standards is described. A half-pel precision processing unit is introduced with an exhaustive block matching unit for integer-pel precision search. The necessary processing power for the exhaustive block matching is implemented with a 1-dimensional array structure utilizing a sub-sampling technique. In comparison with the conventional 2-dimensional array structure, path of the data transfer is so simple that the low power dissipation characteristic is obtained. The problem of communication bandwidth to the frame memory, which is a bottleneck of half-pel precision motion estimation, is solved by introducing a candidate pixel buffer into the inter-processor data transfer. A static latch circuit with conflict free operation is newly developed for reducing the power consumption. This chip is capable of processing NTSC-resolution video in real-time at the 40 MHz operation. The chip integrates about 540 k transistors in the 121 mm² die using 0.8 µm double metal CMOS technology.

Publication: IEICE TRANSACTIONS on Electronics Vol.E77-C No.12 pp.1930-1936

Publication Date: 1994/12/25

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Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)

Category: Processors

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Shin-ichi URAMOTO, Akihiko TAKABATAKE, Mitsuyoshi SUZUKI, Hiroki SAKURAI, Masahiko YOSHIMOTO, "A Half-Pel Precision Motion Estimation Processor for NTSC-Resolution Video" in IEICE TRANSACTIONS on Electronics, vol. E77-C, no. 12, pp. 1930-1936, December 1994, doi: .
Abstract: The hybrid coding with motion compensated prediction and discrete cosine transform (MC+DCT) has been recognized as the standard technique in motion picture coding. In this paper, a motion estimation processor compatible with ITU-T H.261 and MPEG standards is described. A half-pel precision processing unit is introduced with an exhaustive block matching unit for integer-pel precision search. The necessary processing power for the exhaustive block matching is implemented with a 1-dimensional array structure utilizing a sub-sampling technique. In comparison with the conventional 2-dimensional array structure, path of the data transfer is so simple that the low power dissipation characteristic is obtained. The problem of communication bandwidth to the frame memory, which is a bottleneck of half-pel precision motion estimation, is solved by introducing a candidate pixel buffer into the inter-processor data transfer. A static latch circuit with conflict free operation is newly developed for reducing the power consumption. This chip is capable of processing NTSC-resolution video in real-time at the 40 MHz operation. The chip integrates about 540 k transistors in the 121 mm² die using 0.8 µm double metal CMOS technology.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e77-c_12_1930/_p

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@ARTICLE{e77-c_12_1930,
author={Shin-ichi URAMOTO, Akihiko TAKABATAKE, Mitsuyoshi SUZUKI, Hiroki SAKURAI, Masahiko YOSHIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Half-Pel Precision Motion Estimation Processor for NTSC-Resolution Video},
year={1994},
volume={E77-C},
number={12},
pages={1930-1936},
abstract={The hybrid coding with motion compensated prediction and discrete cosine transform (MC+DCT) has been recognized as the standard technique in motion picture coding. In this paper, a motion estimation processor compatible with ITU-T H.261 and MPEG standards is described. A half-pel precision processing unit is introduced with an exhaustive block matching unit for integer-pel precision search. The necessary processing power for the exhaustive block matching is implemented with a 1-dimensional array structure utilizing a sub-sampling technique. In comparison with the conventional 2-dimensional array structure, path of the data transfer is so simple that the low power dissipation characteristic is obtained. The problem of communication bandwidth to the frame memory, which is a bottleneck of half-pel precision motion estimation, is solved by introducing a candidate pixel buffer into the inter-processor data transfer. A static latch circuit with conflict free operation is newly developed for reducing the power consumption. This chip is capable of processing NTSC-resolution video in real-time at the 40 MHz operation. The chip integrates about 540 k transistors in the 121 mm² die using 0.8 µm double metal CMOS technology.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - A Half-Pel Precision Motion Estimation Processor for NTSC-Resolution Video
T2 - IEICE TRANSACTIONS on Electronics
SP - 1930
EP - 1936
AU - Shin-ichi URAMOTO
AU - Akihiko TAKABATAKE
AU - Mitsuyoshi SUZUKI
AU - Hiroki SAKURAI
AU - Masahiko YOSHIMOTO
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 1994
AB - The hybrid coding with motion compensated prediction and discrete cosine transform (MC+DCT) has been recognized as the standard technique in motion picture coding. In this paper, a motion estimation processor compatible with ITU-T H.261 and MPEG standards is described. A half-pel precision processing unit is introduced with an exhaustive block matching unit for integer-pel precision search. The necessary processing power for the exhaustive block matching is implemented with a 1-dimensional array structure utilizing a sub-sampling technique. In comparison with the conventional 2-dimensional array structure, path of the data transfer is so simple that the low power dissipation characteristic is obtained. The problem of communication bandwidth to the frame memory, which is a bottleneck of half-pel precision motion estimation, is solved by introducing a candidate pixel buffer into the inter-processor data transfer. A static latch circuit with conflict free operation is newly developed for reducing the power consumption. This chip is capable of processing NTSC-resolution video in real-time at the 40 MHz operation. The chip integrates about 540 k transistors in the 121 mm² die using 0.8 µm double metal CMOS technology.
ER -