The discrete cosine transform (DCT) has been recognized as one of the standard techniques in image compression. Therefore, a core processor which rapidly computes DCT has become a key component in image compression VLSI's. This paper describes a 100-MHz two-dimensional DCT core processor which is applicable to the real-time processing of HDTV signals. An excellent architecture utilizing a fast DCT algorithm and multiplier accumulators based on distributed arithmetic have contributed to reducing the hardware amount and to enhancing the speed performance. A layout scheme with a column-interleaved memory and a new ROM circuit are introduced for the efficient implementation of memory-based signal processing circuits. Furthermore, mean values of errors generated in the core were minimized to enhance the computational accuracy with the word-length constraints. Consequently, it features the fastest operating speed and the smallest area with its sufficient accuracy satisfying the specifications in CCITT recommendation H.261. The core integrates about 102K transistors, and occupies 21 mm2 using 0.8-µm double-metal CMOS technology.

An MPEG2 video decoder LSI fully compliant with MPEG2 main profile at main level is described. The video decoder LSI is a single chip solution which can implement MPEG2 video decoding with conventional DRAMs. The LSI features an architecture based on dedicated decoding hardware so as to gain the necessary computational power for real-time processing of ITU-R R.601 size video. The variable length decoder (VLD), owing to our "one symbol decoding in one cycle" policy and a special circuit for detecting unique startcodes, achieved bitstream decoding up to 18 Mbps with a normal decoding process. It also realized fast searching for the next start-code in the picture skipping and error recovery processes. The video decoder LSI also features a hierarchical and adaptive control mechanism. This control mechanism decreases the dead time of the decoding circuits and raises the efficiency of data transfer via the local DRAM port. It also contributes to the realization of error concealment and error recovery processes. This chip is capable of processing NTSC-resolution video depicted in MPEG2 MP＠ML in real-time at 27 MHz operation. The chip integrates about 1200 K transistors using 0.5 µm double metal CMOS technology. The feature of the hardware based architecture results in a low power dissipation, and the chip consumes a 1.4 W of power at 3.3 V supply voltage and is housed in a plastic QFP.

The hybrid coding with motion compensated prediction and discrete cosine transform (MC+DCT) has been recognized as the standard technique in motion picture coding. In this paper, a motion estimation processor compatible with ITU-T H.261 and MPEG standards is described. A half-pel precision processing unit is introduced with an exhaustive block matching unit for integer-pel precision search. The necessary processing power for the exhaustive block matching is implemented with a 1-dimensional array structure utilizing a sub-sampling technique. In comparison with the conventional 2-dimensional array structure, path of the data transfer is so simple that the low power dissipation characteristic is obtained. The problem of communication bandwidth to the frame memory, which is a bottleneck of half-pel precision motion estimation, is solved by introducing a candidate pixel buffer into the inter-processor data transfer. A static latch circuit with conflict free operation is newly developed for reducing the power consumption. This chip is capable of processing NTSC-resolution video in real-time at the 40 MHz operation. The chip integrates about 540 k transistors in the 121 mm2 die using 0.8 µm double metal CMOS technology.