A 0.25-µm BiCMOS Technology Using SOR X-Ray Lithography

Shinsuke KONAKA; Hakaru KYURAGI; Toshio KOBAYASHI; Kimiyoshi DEGUCHI; Eiichi YAMAMOTO; Shigehisa OHKI; Yousuke YAMAMOTO

A 0.25-µm BiCMOS Technology Using SOR X-Ray Lithography

Shinsuke KONAKA, Hakaru KYURAGI, Toshio KOBAYASHI, Kimiyoshi DEGUCHI, Eiichi YAMAMOTO, Shigehisa OHKI, Yousuke YAMAMOTO

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A 0.25-µm BiCMOS technology has been developed using three sophisticated technologies; the HSST/BiCMOS device, synchrotron orbital radiation (SOR) X-ray lithography, and an advanced two-level metallization. The HSST/BiCMOS provides a 25.4-ps double-poly bipolar device using High-performance Super Self-Aligned Process Technology (HSST), and a 42 ps/2 V CMOS inverter. SOR lithography allows a 0.18 µm gate and 0.2 µm via-hole patternings by using single-level resists. The metallization process features a new planarization technique of the 0.3-µm first wire, and a selective CVD aluminum plug for a 0.25 µm via-hole with contact resistance lower than 1Ω. These 0.25-µm technologies are used to successfully fabricate a 4 KG 0.25 µm CMOS gate-array LSI on a BiCMOS test chip of 12 mm square, which operates at 58 ps/G at 2 V. This result demonstrates that SOR lithography will pave the way for the fabrication of sub-0.25-µm BiCMOS ULSIs.

Publication: IEICE TRANSACTIONS on Electronics Vol.E77-C No.3 pp.355-361

Publication Date: 1994/03/25

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Type of Manuscript: Special Section PAPER (Special Issue on Quarter Micron Si Device and Process Technologies)

Category: Device Technology

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Shinsuke KONAKA, Hakaru KYURAGI, Toshio KOBAYASHI, Kimiyoshi DEGUCHI, Eiichi YAMAMOTO, Shigehisa OHKI, Yousuke YAMAMOTO, "A 0.25-µm BiCMOS Technology Using SOR X-Ray Lithography" in IEICE TRANSACTIONS on Electronics, vol. E77-C, no. 3, pp. 355-361, March 1994, doi: .
Abstract: A 0.25-µm BiCMOS technology has been developed using three sophisticated technologies; the HSST/BiCMOS device, synchrotron orbital radiation (SOR) X-ray lithography, and an advanced two-level metallization. The HSST/BiCMOS provides a 25.4-ps double-poly bipolar device using High-performance Super Self-Aligned Process Technology (HSST), and a 42 ps/2 V CMOS inverter. SOR lithography allows a 0.18 µm gate and 0.2 µm via-hole patternings by using single-level resists. The metallization process features a new planarization technique of the 0.3-µm first wire, and a selective CVD aluminum plug for a 0.25 µm via-hole with contact resistance lower than 1Ω. These 0.25-µm technologies are used to successfully fabricate a 4 KG 0.25 µm CMOS gate-array LSI on a BiCMOS test chip of 12 mm square, which operates at 58 ps/G at 2 V. This result demonstrates that SOR lithography will pave the way for the fabrication of sub-0.25-µm BiCMOS ULSIs.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e77-c_3_355/_p

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@ARTICLE{e77-c_3_355,
author={Shinsuke KONAKA, Hakaru KYURAGI, Toshio KOBAYASHI, Kimiyoshi DEGUCHI, Eiichi YAMAMOTO, Shigehisa OHKI, Yousuke YAMAMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 0.25-µm BiCMOS Technology Using SOR X-Ray Lithography},
year={1994},
volume={E77-C},
number={3},
pages={355-361},
abstract={A 0.25-µm BiCMOS technology has been developed using three sophisticated technologies; the HSST/BiCMOS device, synchrotron orbital radiation (SOR) X-ray lithography, and an advanced two-level metallization. The HSST/BiCMOS provides a 25.4-ps double-poly bipolar device using High-performance Super Self-Aligned Process Technology (HSST), and a 42 ps/2 V CMOS inverter. SOR lithography allows a 0.18 µm gate and 0.2 µm via-hole patternings by using single-level resists. The metallization process features a new planarization technique of the 0.3-µm first wire, and a selective CVD aluminum plug for a 0.25 µm via-hole with contact resistance lower than 1Ω. These 0.25-µm technologies are used to successfully fabricate a 4 KG 0.25 µm CMOS gate-array LSI on a BiCMOS test chip of 12 mm square, which operates at 58 ps/G at 2 V. This result demonstrates that SOR lithography will pave the way for the fabrication of sub-0.25-µm BiCMOS ULSIs.},
keywords={},
doi={},
ISSN={},
month={March},}

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TY - JOUR
TI - A 0.25-µm BiCMOS Technology Using SOR X-Ray Lithography
T2 - IEICE TRANSACTIONS on Electronics
SP - 355
EP - 361
AU - Shinsuke KONAKA
AU - Hakaru KYURAGI
AU - Toshio KOBAYASHI
AU - Kimiyoshi DEGUCHI
AU - Eiichi YAMAMOTO
AU - Shigehisa OHKI
AU - Yousuke YAMAMOTO
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 1994
AB - A 0.25-µm BiCMOS technology has been developed using three sophisticated technologies; the HSST/BiCMOS device, synchrotron orbital radiation (SOR) X-ray lithography, and an advanced two-level metallization. The HSST/BiCMOS provides a 25.4-ps double-poly bipolar device using High-performance Super Self-Aligned Process Technology (HSST), and a 42 ps/2 V CMOS inverter. SOR lithography allows a 0.18 µm gate and 0.2 µm via-hole patternings by using single-level resists. The metallization process features a new planarization technique of the 0.3-µm first wire, and a selective CVD aluminum plug for a 0.25 µm via-hole with contact resistance lower than 1Ω. These 0.25-µm technologies are used to successfully fabricate a 4 KG 0.25 µm CMOS gate-array LSI on a BiCMOS test chip of 12 mm square, which operates at 58 ps/G at 2 V. This result demonstrates that SOR lithography will pave the way for the fabrication of sub-0.25-µm BiCMOS ULSIs.
ER -