A 120-MHz BiCMOS Superscalar RISC Processor

Shigeya TANAKA; Takashi HOTTA; Fumio MURABAYASHI; Hiromichi YAMADA; Shoji YOSHIDA; Kotaro SHIMAMURA; Koyo KATSURA; Tadaaki BANDOH; Koichi IKEDA; Kenji MATSUBARA; Kouji SAITOU; Tetsuo NAKANO; Teruhisa SHIMIZU; Ryuichi SATOMURA

A 120-MHz BiCMOS Superscalar RISC Processor

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A superscalar RISC processor contains 2.8 million transistors in a die size of 16.2 mm16.5 mm, and utilizes 3.3 V/0.5 µm BiCMOS technology. In order to take advantage of superscalar performance without incurring penalties from a slower clock or a longer pipeline, a tag bit is implemented in the instruction cache to indicate dependency between two instructions. A performance gain of up to 37% is obtained with only a 3.5% area overhead from our superscalar design.

Publication: IEICE TRANSACTIONS on Electronics Vol.E77-C No.5 pp.719-726

Publication Date: 1994/05/25

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Type of Manuscript: Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))

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Shigeya TANAKA
Takashi HOTTA
Fumio MURABAYASHI
Hiromichi YAMADA
Shoji YOSHIDA
Kotaro SHIMAMURA
Koyo KATSURA
Tadaaki BANDOH
Koichi IKEDA
Kenji MATSUBARA
Kouji SAITOU
Tetsuo NAKANO
Teruhisa SHIMIZU
Ryuichi SATOMURA

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Shigeya TANAKA, Takashi HOTTA, Fumio MURABAYASHI, Hiromichi YAMADA, Shoji YOSHIDA, Kotaro SHIMAMURA, Koyo KATSURA, Tadaaki BANDOH, Koichi IKEDA, Kenji MATSUBARA, Kouji SAITOU, Tetsuo NAKANO, Teruhisa SHIMIZU, Ryuichi SATOMURA, "A 120-MHz BiCMOS Superscalar RISC Processor" in IEICE TRANSACTIONS on Electronics, vol. E77-C, no. 5, pp. 719-726, May 1994, doi: .
Abstract: A superscalar RISC processor contains 2.8 million transistors in a die size of 16.2 mm16.5 mm, and utilizes 3.3 V/0.5 µm BiCMOS technology. In order to take advantage of superscalar performance without incurring penalties from a slower clock or a longer pipeline, a tag bit is implemented in the instruction cache to indicate dependency between two instructions. A performance gain of up to 37% is obtained with only a 3.5% area overhead from our superscalar design.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e77-c_5_719/_p

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@ARTICLE{e77-c_5_719,
author={Shigeya TANAKA, Takashi HOTTA, Fumio MURABAYASHI, Hiromichi YAMADA, Shoji YOSHIDA, Kotaro SHIMAMURA, Koyo KATSURA, Tadaaki BANDOH, Koichi IKEDA, Kenji MATSUBARA, Kouji SAITOU, Tetsuo NAKANO, Teruhisa SHIMIZU, Ryuichi SATOMURA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 120-MHz BiCMOS Superscalar RISC Processor},
year={1994},
volume={E77-C},
number={5},
pages={719-726},
abstract={A superscalar RISC processor contains 2.8 million transistors in a die size of 16.2 mm16.5 mm, and utilizes 3.3 V/0.5 µm BiCMOS technology. In order to take advantage of superscalar performance without incurring penalties from a slower clock or a longer pipeline, a tag bit is implemented in the instruction cache to indicate dependency between two instructions. A performance gain of up to 37% is obtained with only a 3.5% area overhead from our superscalar design.},
keywords={},
doi={},
ISSN={},
month={May},}

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TY - JOUR
TI - A 120-MHz BiCMOS Superscalar RISC Processor
T2 - IEICE TRANSACTIONS on Electronics
SP - 719
EP - 726
AU - Shigeya TANAKA
AU - Takashi HOTTA
AU - Fumio MURABAYASHI
AU - Hiromichi YAMADA
AU - Shoji YOSHIDA
AU - Kotaro SHIMAMURA
AU - Koyo KATSURA
AU - Tadaaki BANDOH
AU - Koichi IKEDA
AU - Kenji MATSUBARA
AU - Kouji SAITOU
AU - Tetsuo NAKANO
AU - Teruhisa SHIMIZU
AU - Ryuichi SATOMURA
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1994
AB - A superscalar RISC processor contains 2.8 million transistors in a die size of 16.2 mm16.5 mm, and utilizes 3.3 V/0.5 µm BiCMOS technology. In order to take advantage of superscalar performance without incurring penalties from a slower clock or a longer pipeline, a tag bit is implemented in the instruction cache to indicate dependency between two instructions. A performance gain of up to 37% is obtained with only a 3.5% area overhead from our superscalar design.
ER -