Standby/Active Mode Logic for Sub-1-V Operating ULSI Memory

Daisaburo TAKASHIMA; Shigeyoshi WATANABE; Hiroaki NAKANO; Yukihito OOWAKI; Kazunori OHUCHI; Hiroyuki TANGO

Standby/Active Mode Logic for Sub-1-V Operating ULSI Memory

Daisaburo TAKASHIMA, Shigeyoshi WATANABE, Hiroaki NAKANO, Yukihito OOWAKI, Kazunori OHUCHI, Hiroyuki TANGO

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New gate logics, standby/active mode logic and , for future 1 G/4 Gb DRAM's and battery operated memories are proposed. The circuits realize sub-1-V supply voltage operation with a small 1-µA standby subthreshold leakage current, by allowing 1 mA leakage in the active cycle. Logic is composed of logic gates using dual threshold voltate (V_t) transistors, and it can achieve low standby leakage by adopting high V_t transistors only to transistors which cause a standby leakage current. Logic uses dual supply voltage lines, and reduces the standby leakage by controlling the supply voltage of transistors dissipating a standby leakage current. The gate delay of logic is reduced by 30-37% at the supply voltage of 1.5-1.0 V, and the gate delay of logic is reduced by 40-85% at the supply voltage of 1.5-0.8 V, as compared to that of the conventional CMOS logic.

Publication: IEICE TRANSACTIONS on Electronics Vol.E77-C No.5 pp.771-777

Publication Date: 1994/05/25

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Type of Manuscript: Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))

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Daisaburo TAKASHIMA
Shigeyoshi WATANABE
Hiroaki NAKANO
Yukihito OOWAKI
Kazunori OHUCHI
Hiroyuki TANGO

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Daisaburo TAKASHIMA, Shigeyoshi WATANABE, Hiroaki NAKANO, Yukihito OOWAKI, Kazunori OHUCHI, Hiroyuki TANGO, "Standby/Active Mode Logic for Sub-1-V Operating ULSI Memory" in IEICE TRANSACTIONS on Electronics, vol. E77-C, no. 5, pp. 771-777, May 1994, doi: .
Abstract: New gate logics, standby/active mode logic and , for future 1 G/4 Gb DRAM's and battery operated memories are proposed. The circuits realize sub-1-V supply voltage operation with a small 1-µA standby subthreshold leakage current, by allowing 1 mA leakage in the active cycle. Logic is composed of logic gates using dual threshold voltate (V_t) transistors, and it can achieve low standby leakage by adopting high V_t transistors only to transistors which cause a standby leakage current. Logic uses dual supply voltage lines, and reduces the standby leakage by controlling the supply voltage of transistors dissipating a standby leakage current. The gate delay of logic is reduced by 30-37% at the supply voltage of 1.5-1.0 V, and the gate delay of logic is reduced by 40-85% at the supply voltage of 1.5-0.8 V, as compared to that of the conventional CMOS logic.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e77-c_5_771/_p

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@ARTICLE{e77-c_5_771,
author={Daisaburo TAKASHIMA, Shigeyoshi WATANABE, Hiroaki NAKANO, Yukihito OOWAKI, Kazunori OHUCHI, Hiroyuki TANGO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Standby/Active Mode Logic for Sub-1-V Operating ULSI Memory},
year={1994},
volume={E77-C},
number={5},
pages={771-777},
abstract={New gate logics, standby/active mode logic and , for future 1 G/4 Gb DRAM's and battery operated memories are proposed. The circuits realize sub-1-V supply voltage operation with a small 1-µA standby subthreshold leakage current, by allowing 1 mA leakage in the active cycle. Logic is composed of logic gates using dual threshold voltate (V_t) transistors, and it can achieve low standby leakage by adopting high V_t transistors only to transistors which cause a standby leakage current. Logic uses dual supply voltage lines, and reduces the standby leakage by controlling the supply voltage of transistors dissipating a standby leakage current. The gate delay of logic is reduced by 30-37% at the supply voltage of 1.5-1.0 V, and the gate delay of logic is reduced by 40-85% at the supply voltage of 1.5-0.8 V, as compared to that of the conventional CMOS logic.},
keywords={},
doi={},
ISSN={},
month={May},}

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TY - JOUR
TI - Standby/Active Mode Logic for Sub-1-V Operating ULSI Memory
T2 - IEICE TRANSACTIONS on Electronics
SP - 771
EP - 777
AU - Daisaburo TAKASHIMA
AU - Shigeyoshi WATANABE
AU - Hiroaki NAKANO
AU - Yukihito OOWAKI
AU - Kazunori OHUCHI
AU - Hiroyuki TANGO
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1994
AB - New gate logics, standby/active mode logic and , for future 1 G/4 Gb DRAM's and battery operated memories are proposed. The circuits realize sub-1-V supply voltage operation with a small 1-µA standby subthreshold leakage current, by allowing 1 mA leakage in the active cycle. Logic is composed of logic gates using dual threshold voltate (V_t) transistors, and it can achieve low standby leakage by adopting high V_t transistors only to transistors which cause a standby leakage current. Logic uses dual supply voltage lines, and reduces the standby leakage by controlling the supply voltage of transistors dissipating a standby leakage current. The gate delay of logic is reduced by 30-37% at the supply voltage of 1.5-1.0 V, and the gate delay of logic is reduced by 40-85% at the supply voltage of 1.5-0.8 V, as compared to that of the conventional CMOS logic.
ER -