New gate logics, standby/active mode logic and , for future 1 G/4 Gb DRAM's and battery operated memories are proposed. The circuits realize sub-1-V supply voltage operation with a small 1-µA standby subthreshold leakage current, by allowing 1 mA leakage in the active cycle. Logic is composed of logic gates using dual threshold voltate (Vt) transistors, and it can achieve low standby leakage by adopting high Vt transistors only to transistors which cause a standby leakage current. Logic uses dual supply voltage lines, and reduces the standby leakage by controlling the supply voltage of transistors dissipating a standby leakage current. The gate delay of logic is reduced by 30-37% at the supply voltage of 1.5-1.0 V, and the gate delay of logic is reduced by 40-85% at the supply voltage of 1.5-0.8 V, as compared to that of the conventional CMOS logic.

This letter describes a design methodology for an arithmetic logic unit (ALU) incorporating reconfigurability based on double-gate carbon nanotube field-effect transistors (DG-CNTFETs). The design of a DG-CNTFET with an ambipolar-property-based reconfigurable static logic circuit is simple and straightforward using an ambipolar binary decision diagram (Am-BDD), which represents the cornerstone for the automatic pass transistor logic (PTL) synthesis flows of ambipolar devices. In this work, an ALU with 16 functions is synthesized by the design methodology of a DG-CNTFET-based reconfigurable static logic circuit. Furthermore, it is shown that the proposed ALU is much more flexible and practical than a conventional DG-CNTFET-based reconfigurable ALU.

Hassoune and O'Connor proposed a dynamically reconfigurable dynamic logic circuit (DRDLC) that generates Boolean functions by using double-gate (DG) carbon nanotube (CNT) FETs, which have an ambipolar property. O'Connor et al. proposed a DRDLC that generates 14 Boolean functions asing two Boolean inputs with seven transistors. Furthermore, DRDLCs that generates all 16 Boolean functions have been proposed. In this paper, we focus on the design of a dynamic logic circuit with n Boolean inputs. First, we show a DRDLC that generates the monomial Boolean functions. Next, we propose a DRDLC that generates the whole set of Boolean functions consisting of t terms or less. Finally, we report the number of Boolean functions generated by the proposed DRDLC.

A new memory cell array structure for high density DRAMs is proposed. This new structure is superior to both conventional open bit line and folded bit line structures when the use of isolation merged trench cells, such as FC cell, are considered. The application of this structure to a 16 M bit DRAM cell array design will be also discussed.

An open/folded bit-line (BL) arrangement for scaled DRAM's is proposed. This BL arrangement offers small die size and good array noise immunity. In this arrangement, one BL of an open BL pair is placed in between a folded BL pair, and the sense amplifiers (SA's) for open BL's and those for folded BL's are placed alternately between the memory arrays. This arrangement features a small 6F2 memory cell where F is the device feature size, and a relaxed SA pitch of 6F. The die size of a 64-Mb DRAM can be reduced to 81.6% compared with the one using the conventional folded BL arrangement. The BL-BL coupling noise is reduced to one-half of that of the conventional folded BL arrangement, thanks to the shield effect. Two new circuit techniques, 1) a multiplexer for connecting BL's to SA's, and 2) a binary-to-ternary code converter for the multiplexer have been developed to realize the new BL arrangement.

In order to achieve 3.3-V 1-Gb DRAM and beyond, this paper proposes a new on-chip supply voltage conversion scheme, which converts 3.3-V external supply voltage Vext to lowered 1.5-V internal supply voltage Vint without any power loss within the voltage converter. This scheme connects two identical DRAM circuits in series between Vext and Vss. By operations of two DRAM circuits with the same clock timing, the voltage between two DRAM's, Vint, is automatically fixed to 1/2Vext. Therefore, each upper and lower DRAM circuit can operate at lowered 1/2Vext without use of the conventional voltage converter. This scheme was successfully verified by an experimental system using 4-Mb DRAM's. Utilizing the proposed scheme, power dissipation was reduced by as much as 50% and stable operation was achieved without access speed penalty.

An ultra low voltage CMOS pass-gate logic using body-bias controlled SOI MOSFETs has been developed. The logic is composed of gate-body connected SOI pass-gates and a CMOS buffer with the body-bias controlled by the complementary double-rail input. The full-adder using the proposed logic improved the lowest operation voltage by 27%, compared with the SOI CPL (Complementary Pass-Gate Logic). For a 16 16 bit multiplier, the power-delay product achieved 70 pJ (including 50 pF I/O) at 0.5 V power supply, which was more than 1 order of magnitude improvement over the bulk CPL.

This paper presents a script-based monitoring system for evaluating students' reasoning during problem-solving. Problem-solving processes are equipped with knowledge structures, which are named scripts. A script is a collection of slots for events and provides conceptual dependency between events. Therefore, Script-Based Monitoring Systems (SBMS) can issue assistance to students' requirements and explanations to incorrect activities immediately during problem-solving. The SBMS works as an assistant for circuit analysis. A solution script is designed for the problem-solving process of sinusoidal steady-state network problems by applying loop or branch current analysis. The script is broken up into three scenes: defining variables, deriving equations, and solving equations. After a problem is displayed to a student, she explains her own problem-solving process by sentences and equations. The purpose of the SBMS is to evaluate the student input and determine the control of the dialogue at every step. The evaluation of such events is done by the diagnostic module of the SBMS and the slots of the solution script are filled with the results. As a consequence, the SBMS can hold mixed-initiative dialogues with students. The SBMS is implemented in PROLOG.

For the development of a practical device simulation, it is necessary to solve the large sparse linear equations with a high speed computation of direct solution method. The use of parallel computation methods to solve the linear equations can reduce the CPU time greatly. The Multi Step Diakoptics (MSD) algorithm, is proposed as one of these parallel computation methods with direct solution, which is based on Diakoptics, that is, a tearing-based parallel computation method for sparse linear equations. We have applied the MSD algorithm to device simulation. This letter describes the partition and connection schedules in the MSD algorithm. The evaluation of this algorithm is done using a massively parallel computer with distributed memory (AP1000).

A Unique word-line voltage control method for the 64-Mb DRAM and beyond, which realizes a constant lifetime for thin gate oxide, is proposed. This method controls word-line voltage and compensates reliability degradation in the thin gate oxide for cell-transfer transistors. It keeps constant time-dependent dielectric breakdown (TDDB) lifetime, under any conditions concerning gate oxide thickness fluctuation, temperature variation, and supply voltage variation. This method was successfully implemented in a 64-Mb DRAM to realize high reliability. This chip achieved a 105 times reliability improvement, or a 0.3 1.8-V larger word-line voltage margin to write ONE data into the cell.

Anomalous leakage current which flows between source and drain in thin film SOI MOSFET's is investigated. It is confirmed that the leakage current is caused by enhanced diffusion of the source/drain dopants along the LOCOS-induced crystal defects. Stress analysis by 2D simulation reveals that thinning a buried-oxide effectively suppresses deformation of an SOI film associated with over-oxidation during LOCOS. It is experimentally confirmed that using a SIMOX substrate which has a thinner buried-oxide causes no noticeable deformation of the SOI film nor anomalous leakage current.

A new memory cell arrangement for a gigabit-scale NAND DRAM is proposed. Although the conventional NAND DRAM in which memory cells are connected in series realizes the small die size, it faces a crucial array noise problem in the 1 gigabit generation and beyond because of its inherent noise of the open bitline arrangement. By introducing the new cell arrangement to a NAND DRAM, the folded bitline scheme is realized, resulting in good noise immunity. The basic operation of the proposed folded bitline scheme was successfully verified using the 64 kbit test chip. The die size of the proposed NAND DRAM with the folded bitline scheme (F-NAND DRAM) at the 1 Gbit generation is reduced to 63% of that of the conventional 1 Gbit DRAM with the folded bitline scheme, assuming the bitlines and the wordlines are fabricated with the same pitch. The new 4/4 bitline grouping scheme in which cell data are read out to four neighboring bitlines is also introduced to reduce the bitline-to-bitline coupling noise to half of that of the conventional folded bitline scheme. The array noise of the proposed F-NAND DRAM with the 4/4 bitline grouping scheme at 1 Gbit generation is reduced to 10% of the read-out signal, while that of the conventional NAND DRAM with open bitline scheme is 29%, and that of the conventional DRAM with the folded bitline scheme is 22%.

This paper proposes a small 1/4Vcc bit-line swing scheme and a related sense amplifier scheme for low power 1 V operating DRAM. Using the proposed small bit-line swing scheme, the stress bias of memory cell transistor and capacitor is reduced to half that of the conventional DRAM, resulting in improvement of device reliability. The proposed sense amplifier scheme achieves high speed and stable sensing/restoring operation at 250mV bit-line swing, which is much smaller than threshold voltage. The proposed scheme reduces the total power dissipation of bit-line sensing/restoring operation to 40% of the conventional one. This paper also proposes a small 4F2 size memory cell and a new twisted bit-line scheme. The array noise is reduced to 8.6% of the conventional DRAM.

Multi Step Diakoptics (MSD) is a parallel computation method for solving linear equations. It is used for device simulation, being it executed on a parallel computer. The results show the efficiency of the simulation when the number of nodes that are defined by the five point discretization of semiconductor equations, is over 29.

Among the problems that face ITS designers, the problem of measuring the student knowledge state after concept learning in order to initially adapt a skill acquisition session according to a student's own necessities is a hard one. Typical approaches are the use of some sort of test to assess the student knowledge and choose an initial set of parameters for a session, or use, regardless the particular necessities of a student, a pre-defined set of initial parameters. We consider the fromer to be disrupting for learning and the latter too simple to deal with the broad possibilities that are faced. It is known that students show different behaviors during concept learning depending on the experience, background and actual understanding (the way a student is understanding a concept) during concept learning. Our approach here is to classify the different behaviors through fuzzy proposition and link them with a student model through fuzzy rules to use in an expert system, and with it, select the most suitable problem-solving strategy for each particular student in order to clear his misunderstandings and facilitate the learning of problem-solving skills. The use of probabilistic reasoning (i.e. Bayesian statistics) instead of fuzzy logic is not suitable for the present situation because of the rigidity and precision of the rules that do not allow a proper manipulation of the vagueness involved in the student behavior. We apply this idea to a circuit analysis ITS where the concept learning session is carried out on a Hypertext environment and the skill acquisition session on an interactive problem-solving environment. By tracing the student use of the Hypertext environment we can know the student behavior and use it as a premise in the fuzzy inference.

I. O'Connor et al. have proposed a dynamically reconfigurable dynamic logic circuit (DRDLC) to generate some logic functions by using the double-gate (DG) carbon nanotube (CNT) FETs which have the ambipolar property [1]. This DRDLC consists of seven transistors to generate 14 logic functions which do not include the XOR and XNOR functions. On the other hand, K. Jabeur et al. have proposed a DRDLC to generate the whole set of 16 logic functions including XOR and XNOR by adding 4 or 8 transistors to O'Connor's circuit [5]. In this letter, we propose a DRDLC, which consists of only seven transistors, to generate the whole set of 16 logic functions by using DG-CNTFETs. Finally, we show that the number of transistors can be reduced compared to the conventional DRDLC to generate 16 logic functions.

In this paper, the computational model of Quasi-Ecosystem that is constructed in the way of bottom up, i.e., that consists of herbivores, carnivores and plants is proposed and the simulation result is shown. The behavior pattern of the model is represented by finite state automata. Simple adaptive behavior of animals was observed in this simulation. This indicates that mutation is effective method for self adaptive behavior and the possibility that the model can be used as a framework for autonomous agents.

The high performance network-on-chip (NoC) router using minimal hardware resources to minimize the layout area is very essential for NoC design. In this paper, we have proposed a memory sharing method of a wormhole routed NoC architecture to alleviate the area overhead of a NoC router. In the proposed method, a memory is shared by multiple physical links by using a multi-port memory. In this paper, we have proposed a partial link-sharing method and evaluated the communication performance using the proposed method. It is revealed that the resulted communication performance by the proposed methods is higher than that of the conventional method, and the progress ratio of the 3D-torus network is higher than that of 2D-torus network. It is shown that the improvement of communication performance using partial link sharing method is achieved with slightly increase of hardware cost.

This paper newly estimates the yield suppression for 1.5 V-1 Gbit DRAM caused by threshold voltage variation of MOSFET due to microscopic fluctuations in dopant distributions within the channel region and points out the limitation of the conventional redundancy techniques. The yield suppression is estimated for four main circuit blocks, the memory cell transfer transistor, bit line sense amplifier S/A, I/O line differential amplifier D/A, and the peripheral circuit. It is newly found that for 1.5 V-1 Gbit DRAM due to the effect of the newly estimated threshold voltage variation of MOSFET the bit failures of memory cells become the most dominant failure mode and the failure of D/A which can be ignored for 64 Mbit DRAM level can no longer be neglected. Furthermore, the novel optimized redundancy technique for replacing these failure is described.