Sub-1-µA Dynamic Reference Voltage Generator for Battery-Operated DRAM's

Hitoshi TANAKA; Yoshinobu NAKAGOME; Jun ETOH; Eiji YAMASAKI; Masakazu AOKI; Kazuyuki MIYAZAWA

Sub-1-µA Dynamic Reference Voltage Generator for Battery-Operated DRAM's

Hitoshi TANAKA, Yoshinobu NAKAGOME, Jun ETOH, Eiji YAMASAKI, Masakazu AOKI, Kazuyuki MIYAZAWA

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A new reference voltage generator with ultralow standby current of less than 1 µA is proposed. The features are: 1) a merged scheme of threshold voltage difference generator and voltage-up converter with current mirror circuits, and 2) intermittent activation technique using self-refresh clock for the DRAM. This combination enables the average current to be reduced to 1/100 and the resistance of trimming resistor to be reduced to 1/10 compared to conventional reference voltage generators, while maintaining high accuracy and high stability. The proposed circuit was experimentally evaluated with a test device fabricated using 0.3-µm process. An initial error of less than 4% for 6 trimming steps of the trimming resistor, temperature dependence of less than 370 ppm/ from room temperature to 100, and output noise of less than 12 mV for 1 V_p-p V_cc bumping are achieved. These results are sufficient for achieving high-density battery operated DRAM's with low active and data-retention currents comparable to SRAM's.

Publication: IEICE TRANSACTIONS on Electronics Vol.E77-C No.5 pp.778-783

Publication Date: 1994/05/25

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Type of Manuscript: Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))

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Hitoshi TANAKA
Yoshinobu NAKAGOME
Jun ETOH
Eiji YAMASAKI
Masakazu AOKI
Kazuyuki MIYAZAWA

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Hitoshi TANAKA, Yoshinobu NAKAGOME, Jun ETOH, Eiji YAMASAKI, Masakazu AOKI, Kazuyuki MIYAZAWA, "Sub-1-µA Dynamic Reference Voltage Generator for Battery-Operated DRAM's" in IEICE TRANSACTIONS on Electronics, vol. E77-C, no. 5, pp. 778-783, May 1994, doi: .
Abstract: A new reference voltage generator with ultralow standby current of less than 1 µA is proposed. The features are: 1) a merged scheme of threshold voltage difference generator and voltage-up converter with current mirror circuits, and 2) intermittent activation technique using self-refresh clock for the DRAM. This combination enables the average current to be reduced to 1/100 and the resistance of trimming resistor to be reduced to 1/10 compared to conventional reference voltage generators, while maintaining high accuracy and high stability. The proposed circuit was experimentally evaluated with a test device fabricated using 0.3-µm process. An initial error of less than 4% for 6 trimming steps of the trimming resistor, temperature dependence of less than 370 ppm/ from room temperature to 100, and output noise of less than 12 mV for 1 V_p-p V_cc bumping are achieved. These results are sufficient for achieving high-density battery operated DRAM's with low active and data-retention currents comparable to SRAM's.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e77-c_5_778/_p

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@ARTICLE{e77-c_5_778,
author={Hitoshi TANAKA, Yoshinobu NAKAGOME, Jun ETOH, Eiji YAMASAKI, Masakazu AOKI, Kazuyuki MIYAZAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Sub-1-µA Dynamic Reference Voltage Generator for Battery-Operated DRAM's},
year={1994},
volume={E77-C},
number={5},
pages={778-783},
abstract={A new reference voltage generator with ultralow standby current of less than 1 µA is proposed. The features are: 1) a merged scheme of threshold voltage difference generator and voltage-up converter with current mirror circuits, and 2) intermittent activation technique using self-refresh clock for the DRAM. This combination enables the average current to be reduced to 1/100 and the resistance of trimming resistor to be reduced to 1/10 compared to conventional reference voltage generators, while maintaining high accuracy and high stability. The proposed circuit was experimentally evaluated with a test device fabricated using 0.3-µm process. An initial error of less than 4% for 6 trimming steps of the trimming resistor, temperature dependence of less than 370 ppm/ from room temperature to 100, and output noise of less than 12 mV for 1 V_p-p V_cc bumping are achieved. These results are sufficient for achieving high-density battery operated DRAM's with low active and data-retention currents comparable to SRAM's.},
keywords={},
doi={},
ISSN={},
month={May},}

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TY - JOUR
TI - Sub-1-µA Dynamic Reference Voltage Generator for Battery-Operated DRAM's
T2 - IEICE TRANSACTIONS on Electronics
SP - 778
EP - 783
AU - Hitoshi TANAKA
AU - Yoshinobu NAKAGOME
AU - Jun ETOH
AU - Eiji YAMASAKI
AU - Masakazu AOKI
AU - Kazuyuki MIYAZAWA
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1994
AB - A new reference voltage generator with ultralow standby current of less than 1 µA is proposed. The features are: 1) a merged scheme of threshold voltage difference generator and voltage-up converter with current mirror circuits, and 2) intermittent activation technique using self-refresh clock for the DRAM. This combination enables the average current to be reduced to 1/100 and the resistance of trimming resistor to be reduced to 1/10 compared to conventional reference voltage generators, while maintaining high accuracy and high stability. The proposed circuit was experimentally evaluated with a test device fabricated using 0.3-µm process. An initial error of less than 4% for 6 trimming steps of the trimming resistor, temperature dependence of less than 370 ppm/ from room temperature to 100, and output noise of less than 12 mV for 1 V_p-p V_cc bumping are achieved. These results are sufficient for achieving high-density battery operated DRAM's with low active and data-retention currents comparable to SRAM's.
ER -