State-of-the-art dynamic random access memory (DRAM) technologies are reviewed, focusing on circuit design issues. In addition to density increase, clear trends indicated in recent reports are: (1) low-voltage and low-power DRAMs, e.g. a 1.5-3.6 V 64-Mb DRAM and a 4-Mb DRAM with a 3-µA retention current. Lowering the operating voltage is essential in termss of the reliability of miniaturized devices and the power dissipation of the chip. Besides, the resultant low operating current and the low retention current are keys to meeting the increasing demand for battery-backed or battery-operated DRAMs. Important technologies are high-speed sensing, a high-speed low-power internal voltage generator, a word-line booster, and a refresh timer; (2) High-speed DRAMs with half the access times of standard ones, e.g. 17-ns 4-Mb DRAMs. Many efforts have been made to enhance random and serial access rates, such as direct sensing and on-chip interleaving techniques. In addition to high-speed operation, the movement towards larger bit width requires a means of suppressing the noise increased due to a larger peak current. Waveform control for date-line and output charging current is essential; (3) Yield improvement and test cost reduction techniques, e.g. on-chip ECC, parallel testing, and built-in self-testing. These are becoming more and more important for reducing cost.

A single-chip architecture for three-dimensional (3-D) computer graphics (CG) is discussed assuming portable equipment with a 3-D CG interface. Based on a discussion of chip requirements, an architecture utilizing DRAM technology is proposed. A 31-Mbit, on-chip DRAM cell array allows a full-color, 480640-pixel frame with two 3-D frame buffers for double buffering and one 2-D frame buffer for superimposed or background images. The on-chip pixel generator produces R, G, B, and Z data in a triangular polygon with a zigzag-scan interpolation algorithm. The on-chip frame synthesizer combines data from one of the 3-D buffers with that from the 2-D buffer to produce superimposed or background 2-D images within a 3-D CG image. Parallel alpha-blending and Z-comparison circuits attached to the DRAM cell array provide a high data I/O rate. Estimation of the chip performance assuming the 0.35-µm CMOS design rule shows the chip size, the drawing speed, on-chip data I/O rate, and power dissipation would be 1413.5-mm, 0.25 million polygons/s, 1 gigabyte/s, and 590 mW at a voltage of 3.3 V, respectively. Based on circuit simulations, the chip can run on a 1.5-V dry cell with a drawing speed of 0.125 million polygons/s and a power dissipation of 61 mW. A scaled-down version of the chip which has an 1-kbit DRAM cell array with an attached alpha-blending circuit is being fabricated for evaluation.

An architecture for a high-density nonvolatile memory with ferroelectric capacitors is proposed and simulated. The architecture includes: (1) the operation procedure for DRAM-like memory cells with a Vcc/2 common plate, (2) commands and pin arrangement compatible with those of DRAMs. The resulting ferroelectric memory is expected to show, in addition to nonvolatility, high performance in terms of speed, active power dissipation, and read endurance. In addition, the memory can be handled in the same way as DRAMs. The proposed basic operations are confirmed by using circuit simulations, in which an equivalent circuit model for ferroelectirc capacitors is incorporated. A problem remaining with the architecture is low write endurance due to fatigue along with polarization switching. Designing the reference-voltage generator for 1T1C (one-transistor and one-capacitor) cells, while considering signal reduction along with fatigue, will be another issue for achieving high-density comparable to that of DRAMs.

A new reference voltage generator with ultralow standby current of less than 1 µA is proposed. The features are: 1) a merged scheme of threshold voltage difference generator and voltage-up converter with current mirror circuits, and 2) intermittent activation technique using self-refresh clock for the DRAM. This combination enables the average current to be reduced to 1/100 and the resistance of trimming resistor to be reduced to 1/10 compared to conventional reference voltage generators, while maintaining high accuracy and high stability. The proposed circuit was experimentally evaluated with a test device fabricated using 0.3-µm process. An initial error of less than 4% for 6 trimming steps of the trimming resistor, temperature dependence of less than 370 ppm/ from room temperature to 100, and output noise of less than 12 mV for 1 Vp-p Vcc bumping are achieved. These results are sufficient for achieving high-density battery operated DRAM's with low active and data-retention currents comparable to SRAM's.

A new bus architecture is proposed for reducing the operating power of future ULSI's. This architecture will relieve the constraint of the conventional supply voltage scaling, which makes it difficult to achieve both high speed and a low standby current if the supply voltage is scaled to less than 2 V. It employs new types of bus driver circuits and bus receiver circuits to reduce the bus signal swing while maintaining a low standby current. The bus driver circuit has a source offset configuration through the use of low-VT MOSFET's and an internal supply voltage corresponding to the reduced signal swing. Bus delay is almost halved with this driver when operated at 0.6-V swing and 2-V supply. The bus receiver circuit has a symmetric configuration with two-level conversion circuits, each of which consists of a transmission gate and a cross-coupled latch circuit. Fast level conversion is achieved without increasing the standby current. The combination of new bus driver and bus receiver enables the bus swing to be reduced to one-third that of the conventional architecture while maintaining a high-speed data transmission and a low standby current. A test circuit is designed and fabricated using 0.3-µm processes. The operation of the proposed architecture was verified, and further improvements in the speed performance are expected by device optimization. The proposed architecture is promising for reducing the operating power of future ULSI's.

The dual-sensing-latch circuit proposed here can solve the synchronization problem of the conventional wave-pipelined SRAM, and the proposed source-biased self-resetting circuit reduces both the cycle and access time of cache SRAM's. A 16-kb SRAM using these circuit techniques was designed, and was fabricated with 0.25-µm CMOS technology. Simulation results indicate that this SRAM has a typical clock access time of 2.6 ns at 2.5-V supply voltage and a worst minimum cycle time of 2.6 ns.