A Flexible Search Managing Circuitry for High-Density Dynamic CAMs

Takeshi HAMAMOTO; Tadato YAMAGATA; Masaaki MIHARA; Yasumitsu MURAI; Toshifumi KOBAYASHI; Hideyuki OZAKI

A Flexible Search Managing Circuitry for High-Density Dynamic CAMs

Takeshi HAMAMOTO, Tadato YAMAGATA, Masaaki MIHARA, Yasumitsu MURAI, Toshifumi KOBAYASHI, Hideyuki OZAKI

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New circuit techniques were proposed to realize a high-density and high-performance content addressable memory (CAM). A dynamic register which functions as a status flag, and some logic circuits are organically combined and flexibly perform complex search operations, despite the compact layout area. Any kind of logic operations for the search results, that are AND, OR, INVERT, and the combinations of them, can be implemented in every word simultaneously. These circuits are implemented in an experimental 288 kbit dynamic CAM using 0.8 µm CMOS process technology. We consider these techniques to be indispensable for high-density and high-performance dynamic CAM.

Publication: IEICE TRANSACTIONS on Electronics Vol.E77-C No.8 pp.1377-1384

Publication Date: 1994/08/25

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Type of Manuscript: Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)

Category: General Technology

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Takeshi HAMAMOTO, Tadato YAMAGATA, Masaaki MIHARA, Yasumitsu MURAI, Toshifumi KOBAYASHI, Hideyuki OZAKI, "A Flexible Search Managing Circuitry for High-Density Dynamic CAMs" in IEICE TRANSACTIONS on Electronics, vol. E77-C, no. 8, pp. 1377-1384, August 1994, doi: .
Abstract: New circuit techniques were proposed to realize a high-density and high-performance content addressable memory (CAM). A dynamic register which functions as a status flag, and some logic circuits are organically combined and flexibly perform complex search operations, despite the compact layout area. Any kind of logic operations for the search results, that are AND, OR, INVERT, and the combinations of them, can be implemented in every word simultaneously. These circuits are implemented in an experimental 288 kbit dynamic CAM using 0.8 µm CMOS process technology. We consider these techniques to be indispensable for high-density and high-performance dynamic CAM.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e77-c_8_1377/_p

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@ARTICLE{e77-c_8_1377,
author={Takeshi HAMAMOTO, Tadato YAMAGATA, Masaaki MIHARA, Yasumitsu MURAI, Toshifumi KOBAYASHI, Hideyuki OZAKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Flexible Search Managing Circuitry for High-Density Dynamic CAMs},
year={1994},
volume={E77-C},
number={8},
pages={1377-1384},
abstract={New circuit techniques were proposed to realize a high-density and high-performance content addressable memory (CAM). A dynamic register which functions as a status flag, and some logic circuits are organically combined and flexibly perform complex search operations, despite the compact layout area. Any kind of logic operations for the search results, that are AND, OR, INVERT, and the combinations of them, can be implemented in every word simultaneously. These circuits are implemented in an experimental 288 kbit dynamic CAM using 0.8 µm CMOS process technology. We consider these techniques to be indispensable for high-density and high-performance dynamic CAM.},
keywords={},
doi={},
ISSN={},
month={August},}

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TY - JOUR
TI - A Flexible Search Managing Circuitry for High-Density Dynamic CAMs
T2 - IEICE TRANSACTIONS on Electronics
SP - 1377
EP - 1384
AU - Takeshi HAMAMOTO
AU - Tadato YAMAGATA
AU - Masaaki MIHARA
AU - Yasumitsu MURAI
AU - Toshifumi KOBAYASHI
AU - Hideyuki OZAKI
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 1994
AB - New circuit techniques were proposed to realize a high-density and high-performance content addressable memory (CAM). A dynamic register which functions as a status flag, and some logic circuits are organically combined and flexibly perform complex search operations, despite the compact layout area. Any kind of logic operations for the search results, that are AND, OR, INVERT, and the combinations of them, can be implemented in every word simultaneously. These circuits are implemented in an experimental 288 kbit dynamic CAM using 0.8 µm CMOS process technology. We consider these techniques to be indispensable for high-density and high-performance dynamic CAM.
ER -