An MPEG2 Video Decoder LSI with Hierarchical Control Mechanism

Shin-ichi URAMOTO; Akihiko TAKABATAKE; Takashi HASHIMOTO; Jun TAKEDA; Gen-ichi TANAKA; Tsuyoshi YAMADA; Yukio KODAMA; Atsushi MAEDA; Toshiaki SHIMADA; Shun-ichi SEKIGUCHI; Tokumichi MURAKAMI; Masahiko YOSHIMOTO

An MPEG2 Video Decoder LSI with Hierarchical Control Mechanism

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An MPEG2 video decoder LSI fully compliant with MPEG2 main profile at main level is described. The video decoder LSI is a single chip solution which can implement MPEG2 video decoding with conventional DRAMs. The LSI features an architecture based on dedicated decoding hardware so as to gain the necessary computational power for real-time processing of ITU-R R.601 size video. The variable length decoder (VLD), owing to our "one symbol decoding in one cycle" policy and a special circuit for detecting unique startcodes, achieved bitstream decoding up to 18 Mbps with a normal decoding process. It also realized fast searching for the next start-code in the picture skipping and error recovery processes. The video decoder LSI also features a hierarchical and adaptive control mechanism. This control mechanism decreases the dead time of the decoding circuits and raises the efficiency of data transfer via the local DRAM port. It also contributes to the realization of error concealment and error recovery processes. This chip is capable of processing NTSC-resolution video depicted in MPEG2 MP＠ML in real-time at 27 MHz operation. The chip integrates about 1200 K transistors using 0.5 µm double metal CMOS technology. The feature of the hardware based architecture results in a low power dissipation, and the chip consumes a 1.4 W of power at 3.3 V supply voltage and is housed in a plastic QFP.

Publication: IEICE TRANSACTIONS on Electronics Vol.E78-C No.12 pp.1697-1708

Publication Date: 1995/12/25

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Type of Manuscript: Special Section PAPER (Special Issue on Low-power Analog, Digital LSIs and ASICs for Multimedia)

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Shin-ichi URAMOTO, Akihiko TAKABATAKE, Takashi HASHIMOTO, Jun TAKEDA, Gen-ichi TANAKA, Tsuyoshi YAMADA, Yukio KODAMA, Atsushi MAEDA, Toshiaki SHIMADA, Shun-ichi SEKIGUCHI, Tokumichi MURAKAMI, Masahiko YOSHIMOTO, "An MPEG2 Video Decoder LSI with Hierarchical Control Mechanism" in IEICE TRANSACTIONS on Electronics, vol. E78-C, no. 12, pp. 1697-1708, December 1995, doi: .
Abstract: An MPEG2 video decoder LSI fully compliant with MPEG2 main profile at main level is described. The video decoder LSI is a single chip solution which can implement MPEG2 video decoding with conventional DRAMs. The LSI features an architecture based on dedicated decoding hardware so as to gain the necessary computational power for real-time processing of ITU-R R.601 size video. The variable length decoder (VLD), owing to our "one symbol decoding in one cycle" policy and a special circuit for detecting unique startcodes, achieved bitstream decoding up to 18 Mbps with a normal decoding process. It also realized fast searching for the next start-code in the picture skipping and error recovery processes. The video decoder LSI also features a hierarchical and adaptive control mechanism. This control mechanism decreases the dead time of the decoding circuits and raises the efficiency of data transfer via the local DRAM port. It also contributes to the realization of error concealment and error recovery processes. This chip is capable of processing NTSC-resolution video depicted in MPEG2 MP＠ML in real-time at 27 MHz operation. The chip integrates about 1200 K transistors using 0.5 µm double metal CMOS technology. The feature of the hardware based architecture results in a low power dissipation, and the chip consumes a 1.4 W of power at 3.3 V supply voltage and is housed in a plastic QFP.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e78-c_12_1697/_p

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@ARTICLE{e78-c_12_1697,
author={Shin-ichi URAMOTO, Akihiko TAKABATAKE, Takashi HASHIMOTO, Jun TAKEDA, Gen-ichi TANAKA, Tsuyoshi YAMADA, Yukio KODAMA, Atsushi MAEDA, Toshiaki SHIMADA, Shun-ichi SEKIGUCHI, Tokumichi MURAKAMI, Masahiko YOSHIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={An MPEG2 Video Decoder LSI with Hierarchical Control Mechanism},
year={1995},
volume={E78-C},
number={12},
pages={1697-1708},
abstract={An MPEG2 video decoder LSI fully compliant with MPEG2 main profile at main level is described. The video decoder LSI is a single chip solution which can implement MPEG2 video decoding with conventional DRAMs. The LSI features an architecture based on dedicated decoding hardware so as to gain the necessary computational power for real-time processing of ITU-R R.601 size video. The variable length decoder (VLD), owing to our "one symbol decoding in one cycle" policy and a special circuit for detecting unique startcodes, achieved bitstream decoding up to 18 Mbps with a normal decoding process. It also realized fast searching for the next start-code in the picture skipping and error recovery processes. The video decoder LSI also features a hierarchical and adaptive control mechanism. This control mechanism decreases the dead time of the decoding circuits and raises the efficiency of data transfer via the local DRAM port. It also contributes to the realization of error concealment and error recovery processes. This chip is capable of processing NTSC-resolution video depicted in MPEG2 MP＠ML in real-time at 27 MHz operation. The chip integrates about 1200 K transistors using 0.5 µm double metal CMOS technology. The feature of the hardware based architecture results in a low power dissipation, and the chip consumes a 1.4 W of power at 3.3 V supply voltage and is housed in a plastic QFP.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - An MPEG2 Video Decoder LSI with Hierarchical Control Mechanism
T2 - IEICE TRANSACTIONS on Electronics
SP - 1697
EP - 1708
AU - Shin-ichi URAMOTO
AU - Akihiko TAKABATAKE
AU - Takashi HASHIMOTO
AU - Jun TAKEDA
AU - Gen-ichi TANAKA
AU - Tsuyoshi YAMADA
AU - Yukio KODAMA
AU - Atsushi MAEDA
AU - Toshiaki SHIMADA
AU - Shun-ichi SEKIGUCHI
AU - Tokumichi MURAKAMI
AU - Masahiko YOSHIMOTO
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 1995
AB - An MPEG2 video decoder LSI fully compliant with MPEG2 main profile at main level is described. The video decoder LSI is a single chip solution which can implement MPEG2 video decoding with conventional DRAMs. The LSI features an architecture based on dedicated decoding hardware so as to gain the necessary computational power for real-time processing of ITU-R R.601 size video. The variable length decoder (VLD), owing to our "one symbol decoding in one cycle" policy and a special circuit for detecting unique startcodes, achieved bitstream decoding up to 18 Mbps with a normal decoding process. It also realized fast searching for the next start-code in the picture skipping and error recovery processes. The video decoder LSI also features a hierarchical and adaptive control mechanism. This control mechanism decreases the dead time of the decoding circuits and raises the efficiency of data transfer via the local DRAM port. It also contributes to the realization of error concealment and error recovery processes. This chip is capable of processing NTSC-resolution video depicted in MPEG2 MP＠ML in real-time at 27 MHz operation. The chip integrates about 1200 K transistors using 0.5 µm double metal CMOS technology. The feature of the hardware based architecture results in a low power dissipation, and the chip consumes a 1.4 W of power at 3.3 V supply voltage and is housed in a plastic QFP.
ER -