A 1.5-V 250-MHz to 3.0-V 622-MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Frequency Detector

Harufusa KONDOH, Hiromi NOTANI, Tsutomu YOSHIMURA, Hiroshi SHIBATA, Yoshio MATSUDA

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Summary :

A new approach which implements a simple, high-speed phase detector with precharge logic will be presented. The minimum detectable phase difference is 40 psec, which is less than a half of conventional detectors. A current mode ring oscillator with a complementary-input bias generator has also been developed to enhance the dynamic range of the VCO under a low supply voltage. A fully CMOS PLL was designed using 0.5-µm technology. By virtue of this simple, fast detector, the wide operation range of 250 MHz at 1.5 V to 622 MHz at 3.0 V was achieved by simulation.

Publication
IEICE TRANSACTIONS on Electronics Vol.E78-C No.4 pp.381-388
Publication Date
1995/04/25
Publicized
Online ISSN
DOI
Type of Manuscript
Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits)
Category
Digital Circuits

Authors

Keyword

PLL,  PFD,  VCO,  CMOS,  ATM

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