A new approach which implements a simple, high-speed phase detector with precharge logic will be presented. The minimum detectable phase difference is 40 psec, which is less than a half of conventional detectors. A current mode ring oscillator with a complementary-input bias generator has also been developed to enhance the dynamic range of the VCO under a low supply voltage. A fully CMOS PLL was designed using 0.5-µm technology. By virtue of this simple, fast detector, the wide operation range of 250 MHz at 1.5 V to 622 MHz at 3.0 V was achieved by simulation.
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Harufusa KONDOH, Hiromi NOTANI, Tsutomu YOSHIMURA, Hiroshi SHIBATA, Yoshio MATSUDA, "A 1.5-V 250-MHz to 3.0-V 622-MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Frequency Detector" in IEICE TRANSACTIONS on Electronics,
vol. E78-C, no. 4, pp. 381-388, April 1995, doi: .
Abstract: A new approach which implements a simple, high-speed phase detector with precharge logic will be presented. The minimum detectable phase difference is 40 psec, which is less than a half of conventional detectors. A current mode ring oscillator with a complementary-input bias generator has also been developed to enhance the dynamic range of the VCO under a low supply voltage. A fully CMOS PLL was designed using 0.5-µm technology. By virtue of this simple, fast detector, the wide operation range of 250 MHz at 1.5 V to 622 MHz at 3.0 V was achieved by simulation.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e78-c_4_381/_p
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@ARTICLE{e78-c_4_381,
author={Harufusa KONDOH, Hiromi NOTANI, Tsutomu YOSHIMURA, Hiroshi SHIBATA, Yoshio MATSUDA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 1.5-V 250-MHz to 3.0-V 622-MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Frequency Detector},
year={1995},
volume={E78-C},
number={4},
pages={381-388},
abstract={A new approach which implements a simple, high-speed phase detector with precharge logic will be presented. The minimum detectable phase difference is 40 psec, which is less than a half of conventional detectors. A current mode ring oscillator with a complementary-input bias generator has also been developed to enhance the dynamic range of the VCO under a low supply voltage. A fully CMOS PLL was designed using 0.5-µm technology. By virtue of this simple, fast detector, the wide operation range of 250 MHz at 1.5 V to 622 MHz at 3.0 V was achieved by simulation.},
keywords={},
doi={},
ISSN={},
month={April},}
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TY - JOUR
TI - A 1.5-V 250-MHz to 3.0-V 622-MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Frequency Detector
T2 - IEICE TRANSACTIONS on Electronics
SP - 381
EP - 388
AU - Harufusa KONDOH
AU - Hiromi NOTANI
AU - Tsutomu YOSHIMURA
AU - Hiroshi SHIBATA
AU - Yoshio MATSUDA
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1995
AB - A new approach which implements a simple, high-speed phase detector with precharge logic will be presented. The minimum detectable phase difference is 40 psec, which is less than a half of conventional detectors. A current mode ring oscillator with a complementary-input bias generator has also been developed to enhance the dynamic range of the VCO under a low supply voltage. A fully CMOS PLL was designed using 0.5-µm technology. By virtue of this simple, fast detector, the wide operation range of 250 MHz at 1.5 V to 622 MHz at 3.0 V was achieved by simulation.
ER -