Self-dithered digital delta-sigma modulators (DDSMs) are commonly used in fractional-N frequency synthesizers due to their ability to eliminate unwanted spurs from the synthesizer’s spectra without requiring additional hardware. However, when operating with a low-bit input, self-dithered DDSMs can still suffer from spurious tones at certain inputs. In this paper, we propose a self-dithered MASH 1-1-1-1 structure to mitigate the spur issue in the self-dithered MASH DDSMs. The proposed self-dithered MASH 1-1-1-1 suppresses the spurs with shaped dithering and achieves 4th order noise shaping.

A power-scalable sub-sampling phase-locked loop (SSPLL) is proposed for realizing dual-mode operation; high-performance mode with good phase noise and power-saving mode with moderate phase noise. It is the most efficient way to reduce power consumption by lowering the supply voltage. However, there are several issues with the low-supply millimeter-wave (mmW) SSPLL. This work discusses some techniques, such as a back-gate forward body bias (FBB) technique, in addition to employing a CMOS deeply depleted channel process (DDC).

This paper summarizes the modulation configurations of phase locked loops (PLLs) and their integration in semiconductor circuits, e.g., the input modulation for cellular phones, direct-modulation for low power wireless sensor networks, feedback-loop modulation for high-speed transmission, and two-point modulation for short-range radio transceivers. In this survey, basic configuration examples of integrated circuits for wired and wireless applications which are using the PLL modulation configurations are explained. It is important to select the method for simply and effectively determining the characteristics corresponding to the specific application. The paper also surveys technologies for future PLL design for digitizing of an entire PLL to reduce the phase noise due to a modulation by using a feedback loop with a precise digital phase comparison and a numerically controlled oscillator with high linearity.

In general, since the in-band noise of phase-locked loops (PLLs) is mainly caused by charge pumps (CPs), large-size transistors that occupy a large area are used to improve in-band noise of CPs. With the high demand for low phase noise in recent high-performance communication systems, the issue of the trade-off between occupied area and noise in conventional CPs has become significant. A noise-canceling CP circuit is presented in this paper to mitigate the trade-off between occupied area and noise. The proposed CP can achieve lower noise performance than conventional CPs by performing additional noise cancelation. According to the simulation results, the proposed CP can reduce the current noise to 57% with the same occupied area, or can reduce the occupied area to 22% compared with that of the conventional CPs at the same noise performance. We fabricated a prototype of the proposed CP embedded in a 28-GHz LC-PLL using a 16-nm FinFET process, and 1.2-dB improvement in single sideband integrated phase noise is achieved.

In this paper, an improved charge pump (CP) and a modified nonlinear phase frequency detector (PFD) are designed and fabricated in a 90-nm CMOS process. The CP is optimized with a combination of circuit techniques such as pedestal error cancel scheme to eliminate the charge injection and the other non-ideal characteristics. The nonlinear PFD is based on a modified circuit topology to enhance the acquisition capability of the PLL. The optimized CP and nonlinear PFD are integrated into a Ka-band PLL. The measured output current mismatch ratio of the improved CP is less than 1% when the output voltage Vout fluctuates between 0.2 to 1.1V from a 1.2V power supply. The measured phase error detection range of the modified nonlinear PFD is between -2π and 2π. Owing to the modified CP and PFD, the measured reference spur of the Ka-band PLL frequency synthesizer containing the optimized CP and PFD is only -56.409dBc at 30-GHz at the locked state.

This paper presents a type-I digital ring-based PLL with wide loop bandwidth to lower the ring oscillator's noise contribution. The loop delay due to the D flip-flops at filter's output is compensated in order to lower the noise peak and stably achieve wide loop bandwidth. The input-referred jitter is lowered by using a successive-approximated-register analog-to-digital converter (SAR-ADC)-based sampling phase detector (SPD). A stacked reference buffer is introduced to reduce the transient short-circuit current for low power and low reference spur. The locking issue due to the steady-state phase error in a type-I PLL and the limited range of the phase detector is addressed using a TDC-assisted loop. The loop stability and phase noise are analyzed, suggesting a trade-off for the minimum jitter. The solutions in detail are described. The prototype PLL fabricated in 65 nm CMOS demonstrates 2.0 ps RMS jitter, 3.1 mW power consumption, and 0.067 mm2 area, with 50 MHz reference frequency and 2.0 GHz output frequency.

This paper proposes a pulse-tail-feedback VCO, in which the tail transistor is driven using pulse-shaped voltage signals with rail-to-rail swing. The proposed pulse-tail-feedback (PTFB) VCO relies on reducing the current conduction period of the tail transistor and operating the tail transistors in triode region for reducing the flicker and thermal noise from the active elements. Mathematical analysis and circuit level simulations of the phase noise mechanism in the proposed PTFB-VCO is also presented in this paper for validating the effectiveness of the proposed technique. A prototype LC-VCO with the proposed PTFB technique is fabricated in a standard 180nm CMOS. Laboratory measurement shows a power consumption of 1.35mW from a 1.2V supply at 4.6GHz. The proposed PTFB-VCO achieves a flicker corner of 700Hz, which enables the VCO to maintain a fairly constant figure-of-merit (FoM) of -195dB within a wide offset frequency range of 1kHz-10MHz.

This paper demonstrates a quick start method for Pulse-Width Controlled PLL (PWPLL). Our PLL converts the internal state into digital signals and stores them into a memory before getting into a sleep mode. The wakeup sequence reads the memory and presets the internal state so that our PLL can start the operation with close to the previously locked condition. Since the internal state includes not only the frequency control code but also the phase information, our quick start PLL locks in several clock cycles. A prototype chip fabricated in 0.18µm standard CMOS shows 50ns settling time (4 reference clock cycles), 18.5mW power consumption under 1.8V nominal supply voltage with 105µm×870µm silicon area.

This paper demonstrates a PLL compiler that generates the final GDSII data from a specification of input and output frequencies with PVT corner conditions. A Pulse Width Controlled PLLs (PWPLL) is composed of digital blocks, and thus suitable for being designed using a standard cell library and being layed out with a commercially available place-and-route (P&R) tool. A PWPLL has 8 design parameters. Our PLL compiler decides the 8 parameters and confirms the PLL operation with the following functions: 1) calculates rough parameter values based on an analytical model, 2) generates SPICE and gate-level verilog netlists with given parameter values, 3) runs SPICE simulations and analyzes the waveform, to examine the oscillation frequency or the voltage of specified nodes at a given time, 4) changes the parameter values to an appropriate direction depending on the waveform analyses to obtain the optimized parameter values, 5) generates scripts that can be used in commercial design tools and invokes the tools with the gate-level verilog netlist to get the final LVS/DRC-verified GDSII data from a P&R and a verification tools, and finally 6) generates the necessary characteristic summary sheets from the post-layout SPICE simulations extracted from the GDSII. Our compiler was applied to an 0.18µm standard CMOS technology to design a PLL with 600MHz output, 600/16MHz input frequency, and confirms the PLL operation with 1.2mW power and 85µm×85µm layout area.

We propose a Simulink model of a ring oscillator using saturating integrators. The oscillator's period is tuned via the saturation time of the integrators. Thus, timing jitters due to white and flicker noises are easily introduced into the model, enabling an efficient phase noise evaluation before transistor-level circuit design.

A fully synthesizable all-digital phase-locked loop (AD-PLL) with a stochastic time-to-digital converter (STDC) is proposed in this paper. The whole AD-PLL circuit design is based on only standard cells from digital library, thus the layout of this AD-PLL can be automatically synthesized by a commercial place-and-route (P&R) tool with a foundry-provided standard-cell library. No manual layout and process modification is required in the whole AD-PLL design. In order to solve the delay mismatch issue in the delay-line-based time-to-digital converter (TDC), an STDC employing only standard D flip-flop (DFF) is presented to mitigate the sensitivity to layout mismatch resulted from automatic P&R. For the stochastic TDC, the key idea is to utilize the layout uncertainty due to automatic P&R which follows Gaussian distribution according to statistics theory. Moreover, the fully synthesized STDC can achieve a finer resolution compared to the conventional TDC. Implemented in a 28nm fully depleted silicon on insulator (FDSOI) technology, the fully synthesized PLL consumes only 480µW under 1.0V power supply while operating at 0.9GHz. It achieves a figure of merit (FoM) of -231.1dB with 4.0ps RMS jitter while occupying 0.0055mm2 chip area only.

This paper proposes an on-chip measurement method of PLL through fully digital interface. For the measurement of the PLL transfer function, we modulated the phase of the PLL input in triangular form using Digital-to-Time Converter (DTC) and read out the response by Time-to-Digital Converter (TDC). Combination of the DTC and TDC can obtain the transfer function of the PLL both in the magnitude domain and the phase domain. Since the DTC and TDC can be controlled and observed by digital signals, the measurement can be conducted without any high speed analog signal. Moreover, since the DTC and TDC can be designed symmetrically, the measurement method is robust against Process, Voltage, and Temperature (PVT) variations. At the same time, the employment of the TDC also enables a measurement of the PLL lock range by changing the division ratio of the divider. Two time domain circuits were designed using 180nm CMOS process and the HSPICE simulation results demonstrated the measurement of the transfer function and lock range.

In modern communication systems, it is a critical and challenging issue for existing carrier tracking techniques to achieve near-ideal carrier synchronization without the help of pilot signals in the case of symbol rate sampling and low signal-to-noise ratio (SNR). To overcome this issue, this paper proposes an effective carrier frequency and phase offset tracking scheme which has a robust confluent synchronization architecture whose main components are a digital frequency-locked loop (FLL), a digital phase-locked loop (PLL), a modified symbol hard decision block and some sampling rate conversion blocks. As received signals are sampled at symbol baud rate, this carrier tracking scheme is still able to obtain precise estimated values of carrier synchronization parameters under the condition of very low SNRs. The performance of the proposed carrier synchronization scheme is also evaluated by using Monte-Carlo method. Simulation results confirm the feasibility of this carrier tracking scheme and demonstrate that it ensures that both the rate-3/4 irregular low-density parity-code (LDPC) coded system and the military voice transmission system utilizing the direct sequence spread spectrum (DSSS) technique achieve satisfactory bit-error rate (BER) performance at correspondingly low SNRs.

This report describes an all-digital phase-locked loop (ADPLL) using a temperature compensated settling time reduction technique. The novelty of this work is autonomous oscillation control word estimation without a look-up table or memory circuits. The proposed ADPLL employs a multi-phase digitally controlled oscillator (DCO). In the proposed estimation method, the optimum oscillator tuning word (OTW) is estimated from the DCO frequency characteristic in the setup phase of ADPLL. The proposed ADPLL, which occupies 0.27×0.36mm2, is fabricated by a 65 nm CMOS process. The temperature compensation PLL controller (TCPC) is implemented using an FPGA. Although the proposed method has 20% area overhead, measurement results show that the 47% settling time is reduced. The average settling time at 25°C is 3µs. The average reduction energy is at least 42% from 0°C to 100°C.

In this letter, we establish a model of a digital clock synchronization method for power packet dispatching. The first-order control is carried out to a specified model to achieve the clock synchronization. From the experimental results, it is confirmed that power packets were recognized under autonomous synchronization.

A serial ATA PHY fabricated in a 0.15-µm CMOS process performs the serial ATA operation in an asynchronous transition by using large variation in the reference clock. This technique calibrates a transmission signal frequency by utilizing the received signal. This is achieved by calibrating the divide ratio of a spread-spectrum clock generator (SSCG). This technique enables a serial ATA PHY to use reference oscillators with a production-frequency tolerance of less than 400ppm, i.e., higher than the permissible TX frequency variations (i.e., 350ppm). The calibrated transmission signal achieved a total jitter of 3.9ps.

We present a time-to-digital converter (TDC) achieving sub-picosecond resolution and high precision for all-digital phase-locked-loops (ADPLLs). The basic idea is using a charge pump to translate time interval into charge, and a successive-approximation-register-analog-to-digital converter (SAR-ADC) to quantize the charge. With this less complex configuration, high resolution, high precision, low power, and small area can be achieved all together. We analyzed the noise contribution from the charge pump and describe detailed design and implementation for sizing the capacitor and transistors, with the awareness of noise and linearity. The analysis demonstrates the proposed TDC capable of sub-picosecond resolution and high precision. Two prototype chips were fabricated in 65nm CMOS with 0.06mm2, and 0.018mm2 core areas, respectively. The achieved resolutions are 0.84ps and 0.80ps, in 8-bit and 10-bit range, respectively. The measured single-shot-precisions range from 0.22 to 0.6ps, and from 0.66 to 1.04ps, respectively, showing consistent trends with the analysis. Compared with state-of-the-arts, best performance balance has been achieved.

A monolithic frequency synthesizer with wide tuning range, low phase noise and spurs was realized in 0.13,$mu$m CMOS technology. It consists of an analog PLL, a harmonic-rejection mixer and injection-locked frequency doublers to cover the whole 6--18,GHz frequency range. To achieve a low phase noise performance, a sub-sampling PLL with non-dividers was employed. The synthesizer can achieve phase noise $-$113.7,dBc/Hz@100,kHz in the best case and the reference spur is below $-$60,dBc. The core of the synthesizer consumes about 110,mA*1.2,V.

This paper proposes a radiation-hardened phase-locked loop (RH-PLL) with a switchable dual modular redundancy (DMR) structure. After radiation strikes, unhardened PLLs suffer clock perturbations. Conventional RH-PLLs have been proposed to reduce recovery time after perturbation. However, this recovery still requires tens of clock cycles. Our proposal involves ‘detecting’ and ‘switching’, rather than ‘recovering’ from clock perturbation. Detection speed is crucial for robust perturbation-immunity. We identify types of clock perturbation and then propose a set of detectors to detect each type. With this method, the detectors guarantee high-speed detection that leads to perturbation-immune switching from a radiated clock to an undistorted clock. The proposed RH-PLL was fabricated and then verified with a radiation test on real silicon.

This paper derives a maximum lock range of an injection locked ring oscillator in a direct injection method and presents an injection locked charge-pump phase-locked loop (CPPLL) with a replica of a ring oscillator. The proposed injection-locked PLL separates the injection-locked VCO from the continuous phase-tracking loop of the PLL such that can provide stable lock-state maintenance and tolerance to temperature and supply voltage variation. The measurement results show that the proposed injection-locked PLL can be tolerable to voltage variation of 11.2% in supply voltage of 1.2V. In-band noises of the injection-locked oscillator at offset frequencies of 10kHz and 100kHz are -108.2dBc/Hz and -114.6dBc/Hz, respectively.