A 13-b 10-Msample/s ADC Digitally Calibrated with Oversampling Delta-Sigma Converter

Tzi-Hsiung SHU; Bang-Sup SONG; Kantilal BACRANIA

A 13-b 10-Msample/s ADC Digitally Calibrated with Oversampling Delta-Sigma Converter

Tzi-Hsiung SHU, Bang-Sup SONG, Kantilal BACRANIA

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Two key techniques necessary to digitally calibrate multistep or pipelined converters are demonstrated in a differential 5-V, 13-b, 10-Msample/s analog-to-digital converter (ADC). One technique, called code-error calibration, is to linearize the transfer characteristic of digital-to-analog converters (DAC's) while the other, called gain-error proration, is to evenly distribute interstage gain errors over the full conversion range. The core of the former technique is an oversampling delta-sigma ratio calibrator working synchronously with the converter. This digital calibration process constantly tracks and updates the code errors without interfering with the normal operation. The prototype converter fabricated using a 1.4-µm BiCMOS process consumes 360 mW with a 5-V single supply and exhibits a signal-to-noise ratio of 71 dB and a maximum end-point integral nonlinearity of 1.8 LSB at a 13-b level. The proposed techniques can be incorporated into general multistep or pipelined ADC's without sacrificing the conversion speed.

Publication: IEICE TRANSACTIONS on Electronics Vol.E78-C No.6 pp.691-700

Publication Date: 1995/06/25

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Type of Manuscript: Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995))

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Tzi-Hsiung SHU
Bang-Sup SONG
Kantilal BACRANIA

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Tzi-Hsiung SHU, Bang-Sup SONG, Kantilal BACRANIA, "A 13-b 10-Msample/s ADC Digitally Calibrated with Oversampling Delta-Sigma Converter" in IEICE TRANSACTIONS on Electronics, vol. E78-C, no. 6, pp. 691-700, June 1995, doi: .
Abstract: Two key techniques necessary to digitally calibrate multistep or pipelined converters are demonstrated in a differential 5-V, 13-b, 10-Msample/s analog-to-digital converter (ADC). One technique, called code-error calibration, is to linearize the transfer characteristic of digital-to-analog converters (DAC's) while the other, called gain-error proration, is to evenly distribute interstage gain errors over the full conversion range. The core of the former technique is an oversampling delta-sigma ratio calibrator working synchronously with the converter. This digital calibration process constantly tracks and updates the code errors without interfering with the normal operation. The prototype converter fabricated using a 1.4-µm BiCMOS process consumes 360 mW with a 5-V single supply and exhibits a signal-to-noise ratio of 71 dB and a maximum end-point integral nonlinearity of 1.8 LSB at a 13-b level. The proposed techniques can be incorporated into general multistep or pipelined ADC's without sacrificing the conversion speed.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e78-c_6_691/_p

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@ARTICLE{e78-c_6_691,
author={Tzi-Hsiung SHU, Bang-Sup SONG, Kantilal BACRANIA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 13-b 10-Msample/s ADC Digitally Calibrated with Oversampling Delta-Sigma Converter},
year={1995},
volume={E78-C},
number={6},
pages={691-700},
abstract={Two key techniques necessary to digitally calibrate multistep or pipelined converters are demonstrated in a differential 5-V, 13-b, 10-Msample/s analog-to-digital converter (ADC). One technique, called code-error calibration, is to linearize the transfer characteristic of digital-to-analog converters (DAC's) while the other, called gain-error proration, is to evenly distribute interstage gain errors over the full conversion range. The core of the former technique is an oversampling delta-sigma ratio calibrator working synchronously with the converter. This digital calibration process constantly tracks and updates the code errors without interfering with the normal operation. The prototype converter fabricated using a 1.4-µm BiCMOS process consumes 360 mW with a 5-V single supply and exhibits a signal-to-noise ratio of 71 dB and a maximum end-point integral nonlinearity of 1.8 LSB at a 13-b level. The proposed techniques can be incorporated into general multistep or pipelined ADC's without sacrificing the conversion speed.},
keywords={},
doi={},
ISSN={},
month={June},}

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TY - JOUR
TI - A 13-b 10-Msample/s ADC Digitally Calibrated with Oversampling Delta-Sigma Converter
T2 - IEICE TRANSACTIONS on Electronics
SP - 691
EP - 700
AU - Tzi-Hsiung SHU
AU - Bang-Sup SONG
AU - Kantilal BACRANIA
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1995
AB - Two key techniques necessary to digitally calibrate multistep or pipelined converters are demonstrated in a differential 5-V, 13-b, 10-Msample/s analog-to-digital converter (ADC). One technique, called code-error calibration, is to linearize the transfer characteristic of digital-to-analog converters (DAC's) while the other, called gain-error proration, is to evenly distribute interstage gain errors over the full conversion range. The core of the former technique is an oversampling delta-sigma ratio calibrator working synchronously with the converter. This digital calibration process constantly tracks and updates the code errors without interfering with the normal operation. The prototype converter fabricated using a 1.4-µm BiCMOS process consumes 360 mW with a 5-V single supply and exhibits a signal-to-noise ratio of 71 dB and a maximum end-point integral nonlinearity of 1.8 LSB at a 13-b level. The proposed techniques can be incorporated into general multistep or pipelined ADC's without sacrificing the conversion speed.
ER -