The Asynchronous Transfer Mode (ATM) is considered to be a key technology for B-ISDN. This paper discusses VLSI trends and how VLSI's can be applied to realize ATM switching node systems for B-ISDN. Implementing a practical ATM node system will require the development of technologies such as high-throughput ATM switch LSI's with up to 10 Gb/s capacity and SDH termination technology based on optical fiber transmission. An ATM traffic-handling mechanism with Quality of Service (QoS) controls such as ATM layer performance monitoring, virtual channel handling, usage parameter control, and VP shaping requires several hundred thousand logic gates and several megabytes of high-speed static RAM; VLSI's must be introduced if such mechanisms are to be implemented. ATM node system architecture is based on design principles of a building-block-type structure and hierarchical multiplexing. The basic ATM call handling module, the AHM, is composed mainly of a line termination block and a self-routing switch block; we analyzed this module from the viewpoint of the amount of hardware it requires. Finally, future ATM node systems are discussed on the basis of 0.2-µm VLSI development trends and hardware requirements such as the need for ultrahigh integration of logic gate with memory, multichip modules, and low power dissipation technology.

LSI chips were developed that fit on a switching fabric using chip-to-chip optical interconnections; they have 10-Gb/s serial input and output ports, which facilitates the layout of optically interfaced switching element modules. A test switching modeule composed of these chips was operated at 10.2 Gb/s without bit errors. Ultrahigh-speed switching LSI chips have been developed for a future asynchronous transfer mode (ATM) switching system with an over-Tb/s capacity. Their serial input and output ports facilitate chip-to-chip optical interconnection. Cell-dropper and crosspoint-router LSI chips, composing the core of the switching element, were fabricated by using GaAs LSI technology. A test switching module composed of these chips was operated at 10.2 Gb/s without bit errors.

This paper describes a CMOS serial ling allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 µm CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.

A 256-element associative processing chip is designed for pixel-parallel image processing and machine vision applications. A five-transistor three-state dynamic memory cell is used, and each processing element has 64 trits of memory. Other processing element components include a function generator, an activity register, and connections to a reconfigurable mesh network and a response resolution subsystem. These are implemented with compact circuits designed within memory pitch constraints. The chip was fabricated in a double-poly CCD-CMOS process and characterized as fully functional. A sample image processing application is demonstrated on a four-chip prototype system.

The application trends and key design tradeoffs involved in the design of high performance microprocessors are discussed. In particular the growing importance of improved human interface technology and the need for high-performance, highly-connected systems combined with the need to continue to drive costs lower make design choices very difficult. Technical innovation in the areas of high bandwidth processor-memory interfaces, low-cost multiprocessors and software compatibility are needed in order to continue move forward.

This paper presents a new data cache design, cache-processor coupling, which tightly binds an on-chip data cache with a microprocessor. Parallel architectures and high-speed circuit techniques are developed for speeding address handling process associated with accessing the data cache. The address handling time has been reduced by 51% by these architectures and circuit techniques. On the other hand, newly proposed instructions increase data cache bandwidth by eight times. Excessive power consumption due to the wide-bandwidth data transfer is carefully avoided by newly developed circuit techniques, which reduce dissipation power per bit to 1/26. Simulation study of the proposed architecture and circuit techniques yields a 1.8 ns delay each for address handling, cache access, and register access for a 16 kilobyte direct mapped cache with a 0.4 µm CMOS design rule.

A 3.3 V Phase-Locked-Loop (PLL) clock synthesizer implemented in 0.5 µm CMOS technology is described. The PLL supports internal to external clock frequency ratios of 1, 1.5, 2, 3, and 4 as well as numerous static power down modes for PowerPC^TM microprocessors. The CPU clock lock range spans from 6 to 175 MHz. Lock times below 15 µs, PLL power dissipation below 10 mW as well as phase error and jitter below 100 ps have been measured. The total area of the PLL is 0.52 mm².

This paper presents a novel architecture that provides higher density and lower power dissipation than conventional basecells. The layout of transistors in this small basecell allows the efficient construction of multiplexers with minimal use of programmable layers. The multiplexer can be used to create any 2 input and some 3 input functions in one basecell. Internal fanout, rather than typical output load, defines the size of driver and multiplexer transistors, which can be independently tailored for the desired speed/area/power target. This basecell, which is well suited for implementing datapath elements, has been used to create a 16 16-b multiplier operating at 50 MHz in 314 500 µm² in 0.6 µm technology.

A reduced-swing internal bus scheme is proposed for achieving ultralow-power LSI's. The proposed data-dependent logic swing bus (DDL bus) uses charge sharing between bus wires and an additional bus wire to reduce its voltage swing. With this technique, the power dissipation of the proposed bus is reduced to 1/16 that of a conventional bus when used for a 16-b-wide bus. In addition, a dual-reference sense-amplifying receiver (DRSA receiver) has been developed to convert a reduced-swing bus signal to a CMOS-level signal without loss of noise margin or speed. Experimental circuits fabricated using 0.5-µm CMOS process verify the low-power operation of the proposed bus at an operating frequency of 40 MHz with a supply voltage of 3.3 V.

A programmable digital clock generator that produces a wide range of clock frequencies with fine resolution is described. The clock generator consists of a noise-shaping control loop and a number-controlled oscillator. The generated clock has a time-varying period. When this clock is used as the sampling clock in a switched-capacitor filter (SCF) to set its frequency response, the time-varying period causes nonuniform sampling, which is acceptable under certain conditions that are described. Measured performance of a 2-µm CMOS implementation of the clock generator is presented. Also, measured data for the clock generator driving two SCF's are reported.

A frequency-synthesizing, all-digital phase-locked loop (ADPLL) is fully integrated with a 0.5 µm CMOS microprocessor. The ADPLL has a 50-cycle phase lock, has a gain mechanism independent of process, voltage, and temperature, and is immune to input jitter. A digitally-controlled oscillator (DCO) forms the core of the ADPLL and operates from 50 to 550 MHz, running at 4 the reference clock frequency. The DCO has 16 b of binarily weighted control and achieves LSB resolution under 500 fs.

An asymptotically zero power charge recycling bus (CRB) architecture, featuring virtual stacking of the individual bus-capacitance into a series configuration between supply voltage and ground, has been proposed. This CRB architecture makes it possible to reduce not only each bus-swing but also a total equivalent bus-capacitance of the ultramultibit buses running in parallel. The voltage swing of each bus is given by the recycled charge-supplying from the upper adjacent bus capacitance, instead of the power line. The dramatical power reduction was verified by the simulated and measured data. According to these data, the ultrahigh data rate of 25.6 Gb/s can be achieved while maintaining the power dissipation to be less than 100 mW, which corresponds to less than 10% that of the previously reported 0.9 V suppressed bus-swing scheme, at V_cc = 3.6 V for the bus width of 512 b with the bus-capacitance of 14 pF per bit operating at 50 MHz.

We propose a half-swing clocking scheme that allows us to reduce power consumption of clocking circuitry by as much as 75%, because all the clock signal swings are reduced to half of the LSI supply voltage. The new clocking scheme causes quite small speed degradation, because the random logic circuits in the critical path are still supplied by the full supply voltage. We also propose a clock driver which supplies half-swing clock and generates half V_DD by itself. We confirmed that the half-swing clocking scheme provided 67% power saving in a test chip fabricated with 0.5 µm CMOS device, ideally 75%, in the clocking circuitry, and that the degradation in speed was only 0.5 ns by circuit simulation. The key to the proposed clocking scheme is the concept that the voltage swing is reduced only for clocking circuitry, but is retained for all other circuits in the chip. This results in significant power reduction with minimal speed degradation.

Multichip modules (MCM's) have been actively developed in recent years. They are expected to provide high-performance systems by packing bare chips at a high density. In particular, a thin-film interconnect substrate that can accommodate higher wiring capacity in a few layers is a new option for coping with high pin count and fine pad pitch VLSI's. MCM's require various kinds of technologies including the fabrication processes of interconnect substrates, chip connection methods, electrical design, thermal management, known good die (KGD), and so on. The state of the art of MCM technologies is reviewed and future directions are discussed.

Two key techniques necessary to digitally calibrate multistep or pipelined converters are demonstrated in a differential 5-V, 13-b, 10-Msample/s analog-to-digital converter (ADC). One technique, called code-error calibration, is to linearize the transfer characteristic of digital-to-analog converters (DAC's) while the other, called gain-error proration, is to evenly distribute interstage gain errors over the full conversion range. The core of the former technique is an oversampling delta-sigma ratio calibrator working synchronously with the converter. This digital calibration process constantly tracks and updates the code errors without interfering with the normal operation. The prototype converter fabricated using a 1.4-µm BiCMOS process consumes 360 mW with a 5-V single supply and exhibits a signal-to-noise ratio of 71 dB and a maximum end-point integral nonlinearity of 1.8 LSB at a 13-b level. The proposed techniques can be incorporated into general multistep or pipelined ADC's without sacrificing the conversion speed.

A second-order sigma-delta modulator with a 3-b internal quantizer employing the individual level averaging technique has been designed and implemented in a 1.2 µm CMOS technology. Testing results show no observable harmonic distortion components above the noise floor. Peak S/(N+D) ratio of 91 dB and dynamic range of 96 dB have been achieved at a clock rate of 2.56 MHz for a 20 KHz baseband. No tone is observed in the baseband as the amplitude of a 10 KHz input sine wave is reduced from -0.5 dB to -107 dB below the voltage reference. The active area of the prototype chip is 3.1 mm² and it dissipates 67.5 mW of power from a 5 V supply.

An analog signal processor for hard disk drive servo is described. It performs servo demodulation by means of median peak detection which provides immunity against additive as well as multiplicative noise from the medium, unlike conventional methods. A novel circuit configuration has been employed to implement the median peak detector in an area and power efficient manner. The entire servo processor that includes the demodulator and 10 b A/D and D/A converters has been integrated into a single CMOS integrated circuit.

This paper describes DRAM array driving techniques and the parameter scaling techniques for a low voltage operation using the boosted sense ground (BSG) scheme and further improved methods. A temperature compensation and adjustable internal voltage levels maintain a small subthreshold leakage current of a memory cell transistor (MC-Tr), and a distributed BSG (DBSG) scheme and a column decoded sensing (CDS) scheme achieve the effective scaling. These schemes can set the DRAM array free from a leakage current problem and free them from an influence of temperature variations. Therefore, parameters for the MC-Tr, threshold voltage (V_th), and the boosted voltage for the gate bias can be scaled down, and it is possible to determine the V_th of the MC-Tr easy (0.45 V at K = 0.4) for the satisfaction of the small leakage current, for the high speed and stable operation, and for the high reliability (V_PP is below 2 V_CC). They are applicable to the subquarter micron DRAM's of 256 Mb and more.

A 4-Mb CMOS SRAM with 3.84 µm² TFT load cells is fabricated using 0.25-µm CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V. The use of a current sense amplifier that is insensitive to its offset voltage enables the fast access time. A boosted cell array architecture allows low voltage operation of fast SRAM's using TFT load cells.

The dual-sensing-latch circuit proposed here can solve the synchronization problem of the conventional wave-pipelined SRAM, and the proposed source-biased self-resetting circuit reduces both the cycle and access time of cache SRAM's. A 16-kb SRAM using these circuit techniques was designed, and was fabricated with 0.25-µm CMOS technology. Simulation results indicate that this SRAM has a typical clock access time of 2.6 ns at 2.5-V supply voltage and a worst minimum cycle time of 2.6 ns.

An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-µm² memory cells has been developed using 0.3-µm BiCMOS technology. Two key techniques for achieving ultrahigh speed are an ECL decoder/driver circuit with a BiCMOS inverter and a write-pulse generator with a replica memory cell. These circuit techniques can reduce access time and write-pulse width of the 72-kb RAM macro to 71% and 58% of those of RAM macros with conventional circuits. In order to reduce crosstalk noise for CMOS memory-cell arrays driven at extremely high speeds, a twisted bit-line structure with a normally on MOS equalizer is proposed. These techniques are especially useful for realizing ultrahigh-speed, high-density SRAM's, which have been used as cache and control storages in mainframe computers.

A new CMOS cell design is proposed, analyzed, and implemented in an ASIC macrocell generator to evaluate the performance and reliability of sensing the ground return current produced in the cell during read access. Both single and dual port cell configurations are studied for static noise margin (SNM), writing requirements, and source offset voltage effects. To frame the advantages and differences of the SSS cell, a comparison is made to several conventional SRAM cells. Noise margins are found to be the same or better than conventional cells, and where design allows cell device ratio optimizations, single ended access cells can generate greater SNM than differential cells. The source sensing technique was evaluated by inserting the new cell in a 0.5 µm ASIC memory block and tested on standard ASIC test sets.