A Low-Power Synchronous SRAM Macrocell with Latch-Type Fast Sense Circuits

Nobutaro SHIBATA; Mayumi WATANABE

A Low-Power Synchronous SRAM Macrocell with Latch-Type Fast Sense Circuits

Nobutaro SHIBATA, Mayumi WATANABE

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Low-power circuit techniques for size-configurable SRAM macrocells with wide range of operating frequency are presented. Synchronous specification is employed to drastically reduce the power dissipation for low-frequency applications. Dynamic circuits applied to bitliness and sense circuits contribute to the reduction of power dissipation. To enhance the high-end limitation of operating frequency, a latch-type fast sense circuit and an accurate activation-timing control technique for size-configurable memory macrocells are proposed, and a special CMOS-level input buffer is devised to enable the minimum cycle time of fast synchronous memory macrocells to be evaluated with conventional LSI-test systems. A memory macrocell using these techniques was fabricated with 0.5-µm CMOS technology. Its power consumption strongly depends on the operating frequency, and at 3-MHz suitable for codeless telephone applications is less than 5% that of an asynchronous SRAM designed with full-static CMOS circuits. Its maximum operating frequency at 3.3-V in 100-MHz.

Publication: IEICE TRANSACTIONS on Electronics Vol.E78-C No.7 pp.797-804

Publication Date: 1995/07/25

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Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)

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Nobutaro SHIBATA, Mayumi WATANABE, "A Low-Power Synchronous SRAM Macrocell with Latch-Type Fast Sense Circuits" in IEICE TRANSACTIONS on Electronics, vol. E78-C, no. 7, pp. 797-804, July 1995, doi: .
Abstract: Low-power circuit techniques for size-configurable SRAM macrocells with wide range of operating frequency are presented. Synchronous specification is employed to drastically reduce the power dissipation for low-frequency applications. Dynamic circuits applied to bitliness and sense circuits contribute to the reduction of power dissipation. To enhance the high-end limitation of operating frequency, a latch-type fast sense circuit and an accurate activation-timing control technique for size-configurable memory macrocells are proposed, and a special CMOS-level input buffer is devised to enable the minimum cycle time of fast synchronous memory macrocells to be evaluated with conventional LSI-test systems. A memory macrocell using these techniques was fabricated with 0.5-µm CMOS technology. Its power consumption strongly depends on the operating frequency, and at 3-MHz suitable for codeless telephone applications is less than 5% that of an asynchronous SRAM designed with full-static CMOS circuits. Its maximum operating frequency at 3.3-V in 100-MHz.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e78-c_7_797/_p

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@ARTICLE{e78-c_7_797,
author={Nobutaro SHIBATA, Mayumi WATANABE, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low-Power Synchronous SRAM Macrocell with Latch-Type Fast Sense Circuits},
year={1995},
volume={E78-C},
number={7},
pages={797-804},
abstract={Low-power circuit techniques for size-configurable SRAM macrocells with wide range of operating frequency are presented. Synchronous specification is employed to drastically reduce the power dissipation for low-frequency applications. Dynamic circuits applied to bitliness and sense circuits contribute to the reduction of power dissipation. To enhance the high-end limitation of operating frequency, a latch-type fast sense circuit and an accurate activation-timing control technique for size-configurable memory macrocells are proposed, and a special CMOS-level input buffer is devised to enable the minimum cycle time of fast synchronous memory macrocells to be evaluated with conventional LSI-test systems. A memory macrocell using these techniques was fabricated with 0.5-µm CMOS technology. Its power consumption strongly depends on the operating frequency, and at 3-MHz suitable for codeless telephone applications is less than 5% that of an asynchronous SRAM designed with full-static CMOS circuits. Its maximum operating frequency at 3.3-V in 100-MHz.},
keywords={},
doi={},
ISSN={},
month={July},}

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TY - JOUR
TI - A Low-Power Synchronous SRAM Macrocell with Latch-Type Fast Sense Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 797
EP - 804
AU - Nobutaro SHIBATA
AU - Mayumi WATANABE
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1995
AB - Low-power circuit techniques for size-configurable SRAM macrocells with wide range of operating frequency are presented. Synchronous specification is employed to drastically reduce the power dissipation for low-frequency applications. Dynamic circuits applied to bitliness and sense circuits contribute to the reduction of power dissipation. To enhance the high-end limitation of operating frequency, a latch-type fast sense circuit and an accurate activation-timing control technique for size-configurable memory macrocells are proposed, and a special CMOS-level input buffer is devised to enable the minimum cycle time of fast synchronous memory macrocells to be evaluated with conventional LSI-test systems. A memory macrocell using these techniques was fabricated with 0.5-µm CMOS technology. Its power consumption strongly depends on the operating frequency, and at 3-MHz suitable for codeless telephone applications is less than 5% that of an asynchronous SRAM designed with full-static CMOS circuits. Its maximum operating frequency at 3.3-V in 100-MHz.
ER -