3.0 Gb/s, 272 mW, 8:1 Multiplexer and 4.1 Gb/s, 388 mW, 1:8 Demultiplexer

Kimio UEDA; Nagisa SASAKI; Hisayasu SATO; Shunji KUBO; Koichiro MASHIKO

3.0 Gb/s, 272 mW, 8:1 Multiplexer and 4.1 Gb/s, 388 mW, 1:8 Demultiplexer

Kimio UEDA, Nagisa SASAKI, Hisayasu SATO, Shunji KUBO, Koichiro MASHIKO

Full Text Views

0

Share
Cite this

Summary :

This paper describes an 8:1 multiplexer and a 1:8 demultiplexer for fiber optic transmission systems. These chips incorporate new architectures having a smaller hardware and enabling the use of a lower supply voltage. The multiplexer and the demultiplexer are fabricated using 0.8 µm silicon-bipolar process with a double polysilicon self-aligned structure. The multiplexer operates at a bit rate of up to 3.0 Gb/s, while the demultiplexer operates at a bit rate of up to 4.1 Gb/s. The multiplexer consumes 272 mW and the demultiplexer consumes 388 mW under the power supplies of VEE=-4.0 V and VTT=-2.0 V. These values are the smallest so far above 2.5 Gb/s which is the standard of the Level-16 of the synchronous transfer mode (STM-16).

Publication: IEICE TRANSACTIONS on Electronics Vol.E78-C No.7 pp.866-872

Publication Date: 1995/07/25

Publicized

Online ISSN

DOI

Type of Manuscript: PAPER

Category: Integrated Electronics

Cite this

Copy

Kimio UEDA, Nagisa SASAKI, Hisayasu SATO, Shunji KUBO, Koichiro MASHIKO, "3.0 Gb/s, 272 mW, 8:1 Multiplexer and 4.1 Gb/s, 388 mW, 1:8 Demultiplexer" in IEICE TRANSACTIONS on Electronics, vol. E78-C, no. 7, pp. 866-872, July 1995, doi: .
Abstract: This paper describes an 8:1 multiplexer and a 1:8 demultiplexer for fiber optic transmission systems. These chips incorporate new architectures having a smaller hardware and enabling the use of a lower supply voltage. The multiplexer and the demultiplexer are fabricated using 0.8 µm silicon-bipolar process with a double polysilicon self-aligned structure. The multiplexer operates at a bit rate of up to 3.0 Gb/s, while the demultiplexer operates at a bit rate of up to 4.1 Gb/s. The multiplexer consumes 272 mW and the demultiplexer consumes 388 mW under the power supplies of VEE=-4.0 V and VTT=-2.0 V. These values are the smallest so far above 2.5 Gb/s which is the standard of the Level-16 of the synchronous transfer mode (STM-16).
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e78-c_7_866/_p

Copy

@ARTICLE{e78-c_7_866,
author={Kimio UEDA, Nagisa SASAKI, Hisayasu SATO, Shunji KUBO, Koichiro MASHIKO, },
journal={IEICE TRANSACTIONS on Electronics},
title={3.0 Gb/s, 272 mW, 8:1 Multiplexer and 4.1 Gb/s, 388 mW, 1:8 Demultiplexer},
year={1995},
volume={E78-C},
number={7},
pages={866-872},
abstract={This paper describes an 8:1 multiplexer and a 1:8 demultiplexer for fiber optic transmission systems. These chips incorporate new architectures having a smaller hardware and enabling the use of a lower supply voltage. The multiplexer and the demultiplexer are fabricated using 0.8 µm silicon-bipolar process with a double polysilicon self-aligned structure. The multiplexer operates at a bit rate of up to 3.0 Gb/s, while the demultiplexer operates at a bit rate of up to 4.1 Gb/s. The multiplexer consumes 272 mW and the demultiplexer consumes 388 mW under the power supplies of VEE=-4.0 V and VTT=-2.0 V. These values are the smallest so far above 2.5 Gb/s which is the standard of the Level-16 of the synchronous transfer mode (STM-16).},
keywords={},
doi={},
ISSN={},
month={July},}

Copy

TY - JOUR
TI - 3.0 Gb/s, 272 mW, 8:1 Multiplexer and 4.1 Gb/s, 388 mW, 1:8 Demultiplexer
T2 - IEICE TRANSACTIONS on Electronics
SP - 866
EP - 872
AU - Kimio UEDA
AU - Nagisa SASAKI
AU - Hisayasu SATO
AU - Shunji KUBO
AU - Koichiro MASHIKO
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1995
AB - This paper describes an 8:1 multiplexer and a 1:8 demultiplexer for fiber optic transmission systems. These chips incorporate new architectures having a smaller hardware and enabling the use of a lower supply voltage. The multiplexer and the demultiplexer are fabricated using 0.8 µm silicon-bipolar process with a double polysilicon self-aligned structure. The multiplexer operates at a bit rate of up to 3.0 Gb/s, while the demultiplexer operates at a bit rate of up to 4.1 Gb/s. The multiplexer consumes 272 mW and the demultiplexer consumes 388 mW under the power supplies of VEE=-4.0 V and VTT=-2.0 V. These values are the smallest so far above 2.5 Gb/s which is the standard of the Level-16 of the synchronous transfer mode (STM-16).
ER -