This paper describes a sub 1-V low noise amplifier (LNA) fabricated using a 0.35 µm SOI (silicon on insulator) CMOS process. The SOI devices have high speed performance even at low operating voltage (below 1 V) because of their smaller parasitic capacitance at source and drain than those of bulk MOSs. A body of a MOSFET can be controlled by using a field shield (FS) plate. The transistor body of the LNA is connected to its gate. The threshold voltage of the transistor becomes lower due to the body-biased effect so that a large drain current keeps the gain high, and active-body control improves the 1-dB gain compression point. A gain of 7.0 dB and a Noise Figure (NF) of 3.6 dB are obtained at 1.0 V and 1.9 GHz. The output power at the 1-dB gain compression point is +1.5 dBm. The gain and the output power at the 1-dB gain compression point are higher by 1.2 dB and 2.9 dB respectively than those of a conventionally body-fixed LNA. A 5.5 dB gain is also obtained at the supply voltage of 0.5 V.

This paper describes a flip-flop circuit using a directly controlled emitter-follower with a diode-feedback level stabilizer (DC-DF) and a resistor-feedback level stabilizer (DC-RF) for low-power multi-GHz prescalers. The new flip-flop circuit reduces the emitter-follower current and gains both high-frequency operation and low-power. A dual modulus (4/5) prescaler using this circuit technology was fabricated with a 0.35 µm BiCMOS process. The current draw of the prescaler using the DC-RF is 34% smaller than conventional LCML circuits. The DC-RF prescaler operates at 2.11 GHz with a total current consumption of 1.03 mA. In addition, the circuit operates with a supply voltage of down to 2.4 V by using the resistor level-shift clock-driver.

This paper describes an 8:1 multiplexer and a 1:8 demultiplexer for fiber optic transmission systems. These chips incorporate new architectures having a smaller hardware and enabling the use of a lower supply voltage. The multiplexer and the demultiplexer are fabricated using 0.8 µm silicon-bipolar process with a double polysilicon self-aligned structure. The multiplexer operates at a bit rate of up to 3.0 Gb/s, while the demultiplexer operates at a bit rate of up to 4.1 Gb/s. The multiplexer consumes 272 mW and the demultiplexer consumes 388 mW under the power supplies of VEE=-4.0 V and VTT=-2.0 V. These values are the smallest so far above 2.5 Gb/s which is the standard of the Level-16 of the synchronous transfer mode (STM-16).

We propose a directly controlled emitter-follower circuit with a feedback type level stabilizer for low-voltage, low-power and high-speed bipolar ECL circuits. The emitter-follower circuit employs a current source structure that compensates speed and power for various supply voltage and temperature. The feedback controlled circuit with a small current source stabilizes 'High' level. At a power consumption of 1 mW/gate, the new circuit is 45% faster under the loaded condition (FO1, CL0.5 pF) and has 47% better load driving capability than conventional ECL gates.