Power Reduction of New Divided Layer Bitline Dual Port SRAM with a-Si/Ti Local Wiring Scheme

Koichi MORIKAWA; Jiro IDA

Power Reduction of New Divided Layer Bitline Dual Port SRAM with a-Si/Ti Local Wiring Scheme

Koichi MORIKAWA, Jiro IDA

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The local wiring structure which is known as a technique for reducing junction capacitance due to the area reduction of the Source/Drain junction by the "on-field" contact scheme was constructed. Its effect on speed/power improvement was evaluated with a ring oscillator. A speed improvement of 15% and a 17% reduction in power dissipation was obtained as compared with conventional non-local wiring structures. This technique was applied to a practical device application, that is, a 0.35 µm embedded dual port SRAM used as a buffer memory in an asynchronous transfer mode switch (ATM-SW) LSI. In order to suppress the coupling noise between the write and read bitlines with the small cell realized by the local wiring scheme, a new divided layer 'bitline architecture was developed. As a result, reduction of SRAM macro size of 31% was attained by also applying the local wiring scheme to peripheral circuits, such as decoder, sense amplifier, and driver. A detailed analysis on this embedded dual port SRAM revealed a 15.2% reduction of write port power at 3.3 V. It is also shown that the local wiring technique is more effective with low power supply voltages to allow for further power reduction.

Publication: IEICE TRANSACTIONS on Electronics Vol.E79-C No.12 pp.1713-1719

Publication Date: 1996/12/25

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Type of Manuscript: Special Section PAPER (Special Issue on Low-Power LSI Technologies)

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Koichi MORIKAWA, Jiro IDA, "Power Reduction of New Divided Layer Bitline Dual Port SRAM with a-Si/Ti Local Wiring Scheme" in IEICE TRANSACTIONS on Electronics, vol. E79-C, no. 12, pp. 1713-1719, December 1996, doi: .
Abstract: The local wiring structure which is known as a technique for reducing junction capacitance due to the area reduction of the Source/Drain junction by the "on-field" contact scheme was constructed. Its effect on speed/power improvement was evaluated with a ring oscillator. A speed improvement of 15% and a 17% reduction in power dissipation was obtained as compared with conventional non-local wiring structures. This technique was applied to a practical device application, that is, a 0.35 µm embedded dual port SRAM used as a buffer memory in an asynchronous transfer mode switch (ATM-SW) LSI. In order to suppress the coupling noise between the write and read bitlines with the small cell realized by the local wiring scheme, a new divided layer 'bitline architecture was developed. As a result, reduction of SRAM macro size of 31% was attained by also applying the local wiring scheme to peripheral circuits, such as decoder, sense amplifier, and driver. A detailed analysis on this embedded dual port SRAM revealed a 15.2% reduction of write port power at 3.3 V. It is also shown that the local wiring technique is more effective with low power supply voltages to allow for further power reduction.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e79-c_12_1713/_p

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@ARTICLE{e79-c_12_1713,
author={Koichi MORIKAWA, Jiro IDA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Power Reduction of New Divided Layer Bitline Dual Port SRAM with a-Si/Ti Local Wiring Scheme},
year={1996},
volume={E79-C},
number={12},
pages={1713-1719},
abstract={The local wiring structure which is known as a technique for reducing junction capacitance due to the area reduction of the Source/Drain junction by the "on-field" contact scheme was constructed. Its effect on speed/power improvement was evaluated with a ring oscillator. A speed improvement of 15% and a 17% reduction in power dissipation was obtained as compared with conventional non-local wiring structures. This technique was applied to a practical device application, that is, a 0.35 µm embedded dual port SRAM used as a buffer memory in an asynchronous transfer mode switch (ATM-SW) LSI. In order to suppress the coupling noise between the write and read bitlines with the small cell realized by the local wiring scheme, a new divided layer 'bitline architecture was developed. As a result, reduction of SRAM macro size of 31% was attained by also applying the local wiring scheme to peripheral circuits, such as decoder, sense amplifier, and driver. A detailed analysis on this embedded dual port SRAM revealed a 15.2% reduction of write port power at 3.3 V. It is also shown that the local wiring technique is more effective with low power supply voltages to allow for further power reduction.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - Power Reduction of New Divided Layer Bitline Dual Port SRAM with a-Si/Ti Local Wiring Scheme
T2 - IEICE TRANSACTIONS on Electronics
SP - 1713
EP - 1719
AU - Koichi MORIKAWA
AU - Jiro IDA
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 1996
AB - The local wiring structure which is known as a technique for reducing junction capacitance due to the area reduction of the Source/Drain junction by the "on-field" contact scheme was constructed. Its effect on speed/power improvement was evaluated with a ring oscillator. A speed improvement of 15% and a 17% reduction in power dissipation was obtained as compared with conventional non-local wiring structures. This technique was applied to a practical device application, that is, a 0.35 µm embedded dual port SRAM used as a buffer memory in an asynchronous transfer mode switch (ATM-SW) LSI. In order to suppress the coupling noise between the write and read bitlines with the small cell realized by the local wiring scheme, a new divided layer 'bitline architecture was developed. As a result, reduction of SRAM macro size of 31% was attained by also applying the local wiring scheme to peripheral circuits, such as decoder, sense amplifier, and driver. A detailed analysis on this embedded dual port SRAM revealed a 15.2% reduction of write port power at 3.3 V. It is also shown that the local wiring technique is more effective with low power supply voltages to allow for further power reduction.
ER -