Trends in High-Speed DRAM Architectures

Masaki KUMANOYA; Toshiyuki OGAWA; Yasuhiro KONISHI; Katsumi DOSAKA; Kazuhiro SHIMOTORI

Trends in High-Speed DRAM Architectures

Masaki KUMANOYA, Toshiyuki OGAWA, Yasuhiro KONISHI, Katsumi DOSAKA, Kazuhiro SHIMOTORI

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Various kinds of new architectures have been proposed to enhance operating performance of the DRAM. This paper reviews these architectures including EDO, SDRAM, RDRAM, EDRAM, and CDRAM. The EDO slightly modifies the output control of the conventional DRAM architecture. Other innovative architectures try to enhance the performance by taking advantage of DRAM's internal multiple bits architecture with internal pipeline, parallel-serial conversion, or static buffers/on-chip cache. A quantitative analysis based on an assumption of wait cycles was made to compare PC system performance with some architectures. The calculation indicated the effectiveness of external or on-chip cache. Future trends cover high-speed I/O interface, unified memory architecture, and system integrated memory. The interface includes limited I/O swing such as HSTL and SSTL to realize more than 100MHz operation. Also, Ramlink and SyncLink are briefly reviewed as candidates for next generation interface. Unified memory architecture attempts to save total memory capacity by combining graphics and main memory. Advanced device technology enables system integration which combine system logic and memory. It suggests one potential direction towards system on a chip in the future.

Publication: IEICE TRANSACTIONS on Electronics Vol.E79-C No.4 pp.472-481

Publication Date: 1996/04/25

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Type of Manuscript: Special Section INVITED PAPER (Special Issue on Ultra-High-Speed LSIs)

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Masaki KUMANOYA, Toshiyuki OGAWA, Yasuhiro KONISHI, Katsumi DOSAKA, Kazuhiro SHIMOTORI, "Trends in High-Speed DRAM Architectures" in IEICE TRANSACTIONS on Electronics, vol. E79-C, no. 4, pp. 472-481, April 1996, doi: .
Abstract: Various kinds of new architectures have been proposed to enhance operating performance of the DRAM. This paper reviews these architectures including EDO, SDRAM, RDRAM, EDRAM, and CDRAM. The EDO slightly modifies the output control of the conventional DRAM architecture. Other innovative architectures try to enhance the performance by taking advantage of DRAM's internal multiple bits architecture with internal pipeline, parallel-serial conversion, or static buffers/on-chip cache. A quantitative analysis based on an assumption of wait cycles was made to compare PC system performance with some architectures. The calculation indicated the effectiveness of external or on-chip cache. Future trends cover high-speed I/O interface, unified memory architecture, and system integrated memory. The interface includes limited I/O swing such as HSTL and SSTL to realize more than 100MHz operation. Also, Ramlink and SyncLink are briefly reviewed as candidates for next generation interface. Unified memory architecture attempts to save total memory capacity by combining graphics and main memory. Advanced device technology enables system integration which combine system logic and memory. It suggests one potential direction towards system on a chip in the future.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e79-c_4_472/_p

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@ARTICLE{e79-c_4_472,
author={Masaki KUMANOYA, Toshiyuki OGAWA, Yasuhiro KONISHI, Katsumi DOSAKA, Kazuhiro SHIMOTORI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Trends in High-Speed DRAM Architectures},
year={1996},
volume={E79-C},
number={4},
pages={472-481},
abstract={Various kinds of new architectures have been proposed to enhance operating performance of the DRAM. This paper reviews these architectures including EDO, SDRAM, RDRAM, EDRAM, and CDRAM. The EDO slightly modifies the output control of the conventional DRAM architecture. Other innovative architectures try to enhance the performance by taking advantage of DRAM's internal multiple bits architecture with internal pipeline, parallel-serial conversion, or static buffers/on-chip cache. A quantitative analysis based on an assumption of wait cycles was made to compare PC system performance with some architectures. The calculation indicated the effectiveness of external or on-chip cache. Future trends cover high-speed I/O interface, unified memory architecture, and system integrated memory. The interface includes limited I/O swing such as HSTL and SSTL to realize more than 100MHz operation. Also, Ramlink and SyncLink are briefly reviewed as candidates for next generation interface. Unified memory architecture attempts to save total memory capacity by combining graphics and main memory. Advanced device technology enables system integration which combine system logic and memory. It suggests one potential direction towards system on a chip in the future.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - Trends in High-Speed DRAM Architectures
T2 - IEICE TRANSACTIONS on Electronics
SP - 472
EP - 481
AU - Masaki KUMANOYA
AU - Toshiyuki OGAWA
AU - Yasuhiro KONISHI
AU - Katsumi DOSAKA
AU - Kazuhiro SHIMOTORI
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1996
AB - Various kinds of new architectures have been proposed to enhance operating performance of the DRAM. This paper reviews these architectures including EDO, SDRAM, RDRAM, EDRAM, and CDRAM. The EDO slightly modifies the output control of the conventional DRAM architecture. Other innovative architectures try to enhance the performance by taking advantage of DRAM's internal multiple bits architecture with internal pipeline, parallel-serial conversion, or static buffers/on-chip cache. A quantitative analysis based on an assumption of wait cycles was made to compare PC system performance with some architectures. The calculation indicated the effectiveness of external or on-chip cache. Future trends cover high-speed I/O interface, unified memory architecture, and system integrated memory. The interface includes limited I/O swing such as HSTL and SSTL to realize more than 100MHz operation. Also, Ramlink and SyncLink are briefly reviewed as candidates for next generation interface. Unified memory architecture attempts to save total memory capacity by combining graphics and main memory. Advanced device technology enables system integration which combine system logic and memory. It suggests one potential direction towards system on a chip in the future.
ER -