Ever increasing demand for higher bandwidth memories, which is fueled by multimedia and 3D graphics, seems to be somewhat satisfied with various emerging memory solutions. This paper gives a review of these emerging DRAM architectures and a performance comparison based on a condition to let the readers have some perspectives of the future and optimized graphics systems.

This paper describes a system integrated memory with direct interface to CPU which integrates an SRAM, a DRAM, and control circuitry, including a tag memory (TAG). This memory realizes a computer system without glue chips, and thus enables a computer system which is low cost, low power, and compact size, but still with sufficient performance. And fast clock cycle time and access time is realized using a newly proposed clock driver and internal signal generator. This memory is fabricated with a quad-polysilicon double-metal 0.55-µm CMOS process which is the same as used in a conventional 16-Mb DRAM. The chip size of 145.3mm2 is only a 12% increase over the conventional 16-Mb DRAM. The maximum operating frequency is 90-MHz and the operating current at cache-hit is 156-mA. This memory is suitable for various types of computer systems such as personal digital assistants(PDA's), personal computer systems, and embedded controller applications.

Various kinds of new architectures have been proposed to enhance operating performance of the DRAM. This paper reviews these architectures including EDO, SDRAM, RDRAM, EDRAM, and CDRAM. The EDO slightly modifies the output control of the conventional DRAM architecture. Other innovative architectures try to enhance the performance by taking advantage of DRAM's internal multiple bits architecture with internal pipeline, parallel-serial conversion, or static buffers/on-chip cache. A quantitative analysis based on an assumption of wait cycles was made to compare PC system performance with some architectures. The calculation indicated the effectiveness of external or on-chip cache. Future trends cover high-speed I/O interface, unified memory architecture, and system integrated memory. The interface includes limited I/O swing such as HSTL and SSTL to realize more than 100MHz operation. Also, Ramlink and SyncLink are briefly reviewed as candidates for next generation interface. Unified memory architecture attempts to save total memory capacity by combining graphics and main memory. Advanced device technology enables system integration which combine system logic and memory. It suggests one potential direction towards system on a chip in the future.

In this paper, we propose an access control protocol method that maintains the communication quality of various applications and reduces packet loss of multicasts in wireless local area networks. Multicast transmission may facilitate effective bandwidth use because packets are simultaneously delivered to more than one mobile station by a single transmission. However, because multicast transmissions does not have a retransmission function, communication quality deteriorates because of packet collisions and interference waves from other systems. Moreover, although multicasts are not considered, the communication quality of each application is guaranteed by a priority control method known as enhanced distributed channel access in IEEE802.11e. The proposed method avoids both these issues. Specifically, because the proposed method first transmits the clear-to-send-to-self frame, the multicast packet avoids collision with the unicast packet. We validate the proposed method by computer simulation in an environment with traffic congestion and interference waves. The results show a reduction in multicast packet loss of approximately 20% and a higher multicast throughput improvement compared to conventional methods. Moreover, the proposed method can assure improve multicast communication quality without affecting other applications.