A 2.6-Gbps/pin SIMOX-CMOS Low-Voltage-Swing Interface Circuit

Yusuke OHTOMO; Masafumi NOGAWA; Masayuki INO

A 2.6-Gbps/pin SIMOX-CMOS Low-Voltage-Swing Interface Circuit

Yusuke OHTOMO, Masafumi NOGAWA, Masayuki INO

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This paper describes a new active pull-up (APU) interface for high-speed point-to-point transmission. The APU circuit is used to speed up a low-power-consumption open-drain-type interface. It pulls up the output at a fixed duration and this limiting of the pull-up duration prevents the pull-up operation from going into a counter phase at over 1-Gbps operation. Measurements of test chips fabricated with 0.25-µm bulk CMOS show. 1.7-Gbps error-free operation for the APU interface and 1.2-Gbps operation for the open-drain-type interface: The APU interface is 1.4 faster than the open-drain type. The application of a 0.25-µm SIMOX-CMOS device to the APU interface increases the bit rate 1.5 times compared with 0.25-µm bulk CMOS. Altogether the interface covers the bit rate of 2.4 Gbps, which is a layer of the communication hierarchy. The APU interface circuit can be applied to large-pin-count LSIs because of its full-CMOS single-rail structure.

Publication: IEICE TRANSACTIONS on Electronics Vol.E79-C No.4 pp.524-529

Publication Date: 1996/04/25

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Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed LSIs)

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Yusuke OHTOMO, Masafumi NOGAWA, Masayuki INO, "A 2.6-Gbps/pin SIMOX-CMOS Low-Voltage-Swing Interface Circuit" in IEICE TRANSACTIONS on Electronics, vol. E79-C, no. 4, pp. 524-529, April 1996, doi: .
Abstract: This paper describes a new active pull-up (APU) interface for high-speed point-to-point transmission. The APU circuit is used to speed up a low-power-consumption open-drain-type interface. It pulls up the output at a fixed duration and this limiting of the pull-up duration prevents the pull-up operation from going into a counter phase at over 1-Gbps operation. Measurements of test chips fabricated with 0.25-µm bulk CMOS show. 1.7-Gbps error-free operation for the APU interface and 1.2-Gbps operation for the open-drain-type interface: The APU interface is 1.4 faster than the open-drain type. The application of a 0.25-µm SIMOX-CMOS device to the APU interface increases the bit rate 1.5 times compared with 0.25-µm bulk CMOS. Altogether the interface covers the bit rate of 2.4 Gbps, which is a layer of the communication hierarchy. The APU interface circuit can be applied to large-pin-count LSIs because of its full-CMOS single-rail structure.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e79-c_4_524/_p

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@ARTICLE{e79-c_4_524,
author={Yusuke OHTOMO, Masafumi NOGAWA, Masayuki INO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 2.6-Gbps/pin SIMOX-CMOS Low-Voltage-Swing Interface Circuit},
year={1996},
volume={E79-C},
number={4},
pages={524-529},
abstract={This paper describes a new active pull-up (APU) interface for high-speed point-to-point transmission. The APU circuit is used to speed up a low-power-consumption open-drain-type interface. It pulls up the output at a fixed duration and this limiting of the pull-up duration prevents the pull-up operation from going into a counter phase at over 1-Gbps operation. Measurements of test chips fabricated with 0.25-µm bulk CMOS show. 1.7-Gbps error-free operation for the APU interface and 1.2-Gbps operation for the open-drain-type interface: The APU interface is 1.4 faster than the open-drain type. The application of a 0.25-µm SIMOX-CMOS device to the APU interface increases the bit rate 1.5 times compared with 0.25-µm bulk CMOS. Altogether the interface covers the bit rate of 2.4 Gbps, which is a layer of the communication hierarchy. The APU interface circuit can be applied to large-pin-count LSIs because of its full-CMOS single-rail structure.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - A 2.6-Gbps/pin SIMOX-CMOS Low-Voltage-Swing Interface Circuit
T2 - IEICE TRANSACTIONS on Electronics
SP - 524
EP - 529
AU - Yusuke OHTOMO
AU - Masafumi NOGAWA
AU - Masayuki INO
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1996
AB - This paper describes a new active pull-up (APU) interface for high-speed point-to-point transmission. The APU circuit is used to speed up a low-power-consumption open-drain-type interface. It pulls up the output at a fixed duration and this limiting of the pull-up duration prevents the pull-up operation from going into a counter phase at over 1-Gbps operation. Measurements of test chips fabricated with 0.25-µm bulk CMOS show. 1.7-Gbps error-free operation for the APU interface and 1.2-Gbps operation for the open-drain-type interface: The APU interface is 1.4 faster than the open-drain type. The application of a 0.25-µm SIMOX-CMOS device to the APU interface increases the bit rate 1.5 times compared with 0.25-µm bulk CMOS. Altogether the interface covers the bit rate of 2.4 Gbps, which is a layer of the communication hierarchy. The APU interface circuit can be applied to large-pin-count LSIs because of its full-CMOS single-rail structure.
ER -