A Crossing Charge Recycle Refresh Scheme with a Separated Driver Sense-Amplifier for Gb DRAMs

Isao NARITAKE; Tadahiko SUGIBAYASHI; Satoshi UTSUGI; Tatsunori MUROTANI

A Crossing Charge Recycle Refresh Scheme with a Separated Driver Sense-Amplifier for Gb DRAMs

Isao NARITAKE, Tadahiko SUGIBAYASHI, Satoshi UTSUGI, Tatsunori MUROTANI

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A crossing charge recycle refresh(CCRR) scheme and a serial charge recycle refresh(SCRR) scheme are proposed for the large capacity DRAMs with hierarchical bit-line architecture to reduce main bit-line charging current. A separated driver sense-amplifier(SDSA) circuit is essential to realize this scheme because it features 11 times shorter charge transfer period than that of conventional sense-amplifiers. These circuits are applied to an experimental 1-Gb DRAM, which achieves reduction of main bit-line charging current to 37.5%.

Publication: IEICE TRANSACTIONS on Electronics Vol.E79-C No.6 pp.787-791

Publication Date: 1996/06/25

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Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology)

Category: Dynamic RAMs

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Isao NARITAKE, Tadahiko SUGIBAYASHI, Satoshi UTSUGI, Tatsunori MUROTANI, "A Crossing Charge Recycle Refresh Scheme with a Separated Driver Sense-Amplifier for Gb DRAMs" in IEICE TRANSACTIONS on Electronics, vol. E79-C, no. 6, pp. 787-791, June 1996, doi: .
Abstract: A crossing charge recycle refresh(CCRR) scheme and a serial charge recycle refresh(SCRR) scheme are proposed for the large capacity DRAMs with hierarchical bit-line architecture to reduce main bit-line charging current. A separated driver sense-amplifier(SDSA) circuit is essential to realize this scheme because it features 11 times shorter charge transfer period than that of conventional sense-amplifiers. These circuits are applied to an experimental 1-Gb DRAM, which achieves reduction of main bit-line charging current to 37.5%.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e79-c_6_787/_p

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@ARTICLE{e79-c_6_787,
author={Isao NARITAKE, Tadahiko SUGIBAYASHI, Satoshi UTSUGI, Tatsunori MUROTANI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Crossing Charge Recycle Refresh Scheme with a Separated Driver Sense-Amplifier for Gb DRAMs},
year={1996},
volume={E79-C},
number={6},
pages={787-791},
abstract={A crossing charge recycle refresh(CCRR) scheme and a serial charge recycle refresh(SCRR) scheme are proposed for the large capacity DRAMs with hierarchical bit-line architecture to reduce main bit-line charging current. A separated driver sense-amplifier(SDSA) circuit is essential to realize this scheme because it features 11 times shorter charge transfer period than that of conventional sense-amplifiers. These circuits are applied to an experimental 1-Gb DRAM, which achieves reduction of main bit-line charging current to 37.5%.},
keywords={},
doi={},
ISSN={},
month={June},}

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TY - JOUR
TI - A Crossing Charge Recycle Refresh Scheme with a Separated Driver Sense-Amplifier for Gb DRAMs
T2 - IEICE TRANSACTIONS on Electronics
SP - 787
EP - 791
AU - Isao NARITAKE
AU - Tadahiko SUGIBAYASHI
AU - Satoshi UTSUGI
AU - Tatsunori MUROTANI
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1996
AB - A crossing charge recycle refresh(CCRR) scheme and a serial charge recycle refresh(SCRR) scheme are proposed for the large capacity DRAMs with hierarchical bit-line architecture to reduce main bit-line charging current. A separated driver sense-amplifier(SDSA) circuit is essential to realize this scheme because it features 11 times shorter charge transfer period than that of conventional sense-amplifiers. These circuits are applied to an experimental 1-Gb DRAM, which achieves reduction of main bit-line charging current to 37.5%.
ER -