Folded Bitline Architecture for a Gigabit-Scale NAND DRAM

Shinichiro SHIRATAKE; Daisaburo TAKASHIMA; Takehiro HASEGAWA; Hiroaki NAKANO; Yukihito OOWAKI; Shigeyoshi WATANABE; Takashi OHSAWA; Kazunori OHUCHI

Folded Bitline Architecture for a Gigabit-Scale NAND DRAM

Shinichiro SHIRATAKE, Daisaburo TAKASHIMA, Takehiro HASEGAWA, Hiroaki NAKANO, Yukihito OOWAKI, Shigeyoshi WATANABE, Takashi OHSAWA, Kazunori OHUCHI

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A new memory cell arrangement for a gigabit-scale NAND DRAM is proposed. Although the conventional NAND DRAM in which memory cells are connected in series realizes the small die size, it faces a crucial array noise problem in the 1 gigabit generation and beyond because of its inherent noise of the open bitline arrangement. By introducing the new cell arrangement to a NAND DRAM, the folded bitline scheme is realized, resulting in good noise immunity. The basic operation of the proposed folded bitline scheme was successfully verified using the 64 kbit test chip. The die size of the proposed NAND DRAM with the folded bitline scheme (F-NAND DRAM) at the 1 Gbit generation is reduced to 63% of that of the conventional 1 Gbit DRAM with the folded bitline scheme, assuming the bitlines and the wordlines are fabricated with the same pitch. The new 4/4 bitline grouping scheme in which cell data are read out to four neighboring bitlines is also introduced to reduce the bitline-to-bitline coupling noise to half of that of the conventional folded bitline scheme. The array noise of the proposed F-NAND DRAM with the 4/4 bitline grouping scheme at 1 Gbit generation is reduced to 10% of the read-out signal, while that of the conventional NAND DRAM with open bitline scheme is 29%, and that of the conventional DRAM with the folded bitline scheme is 22%.

Publication: IEICE TRANSACTIONS on Electronics Vol.E80-C No.4 pp.573-581

Publication Date: 1997/04/25

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Type of Manuscript: Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)

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Shinichiro SHIRATAKE, Daisaburo TAKASHIMA, Takehiro HASEGAWA, Hiroaki NAKANO, Yukihito OOWAKI, Shigeyoshi WATANABE, Takashi OHSAWA, Kazunori OHUCHI, "Folded Bitline Architecture for a Gigabit-Scale NAND DRAM" in IEICE TRANSACTIONS on Electronics, vol. E80-C, no. 4, pp. 573-581, April 1997, doi: .
Abstract: A new memory cell arrangement for a gigabit-scale NAND DRAM is proposed. Although the conventional NAND DRAM in which memory cells are connected in series realizes the small die size, it faces a crucial array noise problem in the 1 gigabit generation and beyond because of its inherent noise of the open bitline arrangement. By introducing the new cell arrangement to a NAND DRAM, the folded bitline scheme is realized, resulting in good noise immunity. The basic operation of the proposed folded bitline scheme was successfully verified using the 64 kbit test chip. The die size of the proposed NAND DRAM with the folded bitline scheme (F-NAND DRAM) at the 1 Gbit generation is reduced to 63% of that of the conventional 1 Gbit DRAM with the folded bitline scheme, assuming the bitlines and the wordlines are fabricated with the same pitch. The new 4/4 bitline grouping scheme in which cell data are read out to four neighboring bitlines is also introduced to reduce the bitline-to-bitline coupling noise to half of that of the conventional folded bitline scheme. The array noise of the proposed F-NAND DRAM with the 4/4 bitline grouping scheme at 1 Gbit generation is reduced to 10% of the read-out signal, while that of the conventional NAND DRAM with open bitline scheme is 29%, and that of the conventional DRAM with the folded bitline scheme is 22%.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e80-c_4_573/_p

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@ARTICLE{e80-c_4_573,
author={Shinichiro SHIRATAKE, Daisaburo TAKASHIMA, Takehiro HASEGAWA, Hiroaki NAKANO, Yukihito OOWAKI, Shigeyoshi WATANABE, Takashi OHSAWA, Kazunori OHUCHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Folded Bitline Architecture for a Gigabit-Scale NAND DRAM},
year={1997},
volume={E80-C},
number={4},
pages={573-581},
abstract={A new memory cell arrangement for a gigabit-scale NAND DRAM is proposed. Although the conventional NAND DRAM in which memory cells are connected in series realizes the small die size, it faces a crucial array noise problem in the 1 gigabit generation and beyond because of its inherent noise of the open bitline arrangement. By introducing the new cell arrangement to a NAND DRAM, the folded bitline scheme is realized, resulting in good noise immunity. The basic operation of the proposed folded bitline scheme was successfully verified using the 64 kbit test chip. The die size of the proposed NAND DRAM with the folded bitline scheme (F-NAND DRAM) at the 1 Gbit generation is reduced to 63% of that of the conventional 1 Gbit DRAM with the folded bitline scheme, assuming the bitlines and the wordlines are fabricated with the same pitch. The new 4/4 bitline grouping scheme in which cell data are read out to four neighboring bitlines is also introduced to reduce the bitline-to-bitline coupling noise to half of that of the conventional folded bitline scheme. The array noise of the proposed F-NAND DRAM with the 4/4 bitline grouping scheme at 1 Gbit generation is reduced to 10% of the read-out signal, while that of the conventional NAND DRAM with open bitline scheme is 29%, and that of the conventional DRAM with the folded bitline scheme is 22%.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - Folded Bitline Architecture for a Gigabit-Scale NAND DRAM
T2 - IEICE TRANSACTIONS on Electronics
SP - 573
EP - 581
AU - Shinichiro SHIRATAKE
AU - Daisaburo TAKASHIMA
AU - Takehiro HASEGAWA
AU - Hiroaki NAKANO
AU - Yukihito OOWAKI
AU - Shigeyoshi WATANABE
AU - Takashi OHSAWA
AU - Kazunori OHUCHI
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E80-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1997
AB - A new memory cell arrangement for a gigabit-scale NAND DRAM is proposed. Although the conventional NAND DRAM in which memory cells are connected in series realizes the small die size, it faces a crucial array noise problem in the 1 gigabit generation and beyond because of its inherent noise of the open bitline arrangement. By introducing the new cell arrangement to a NAND DRAM, the folded bitline scheme is realized, resulting in good noise immunity. The basic operation of the proposed folded bitline scheme was successfully verified using the 64 kbit test chip. The die size of the proposed NAND DRAM with the folded bitline scheme (F-NAND DRAM) at the 1 Gbit generation is reduced to 63% of that of the conventional 1 Gbit DRAM with the folded bitline scheme, assuming the bitlines and the wordlines are fabricated with the same pitch. The new 4/4 bitline grouping scheme in which cell data are read out to four neighboring bitlines is also introduced to reduce the bitline-to-bitline coupling noise to half of that of the conventional folded bitline scheme. The array noise of the proposed F-NAND DRAM with the 4/4 bitline grouping scheme at 1 Gbit generation is reduced to 10% of the read-out signal, while that of the conventional NAND DRAM with open bitline scheme is 29%, and that of the conventional DRAM with the folded bitline scheme is 22%.
ER -