Adaptive Biasing Folded Cascode CMOS OP Amp with Continuous-Time Push-Pull CMFB Scheme

Jae-Yoon SIM; Cheol-Hee LEE; Won-Chang JEONG; Hong-June PARK

Adaptive Biasing Folded Cascode CMOS OP Amp with Continuous-Time Push-Pull CMFB Scheme

Jae-Yoon SIM, Cheol-Hee LEE, Won-Chang JEONG, Hong-June PARK

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A fully differential folded cascode CMOS OP amp is combined with an adaptive bias OTA to increase the slew rate, and a continuous-time CMFB circuit with a push-pull type combination of a NMOS input and a PMOS input differential amplifiers is used to maximize the output voltage swing. The fabricated OP amp using a 0.8 µm digital CMOS process gives more than three times improvement in slew rate with a 15% increase in DC power consumption and a 7.5% increase in chip area compared to the conventional OP amp fabricated on the same die. The output voltage swing was measured to be -0.75 V -0.7 V at the supply voltage of +/-1.2 V.

Publication: IEICE TRANSACTIONS on Electronics Vol.E80-C No.9 pp.1203-1210

Publication Date: 1997/09/25

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Category: Electronic Circuits

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Jae-Yoon SIM, Cheol-Hee LEE, Won-Chang JEONG, Hong-June PARK, "Adaptive Biasing Folded Cascode CMOS OP Amp with Continuous-Time Push-Pull CMFB Scheme" in IEICE TRANSACTIONS on Electronics, vol. E80-C, no. 9, pp. 1203-1210, September 1997, doi: .
Abstract: A fully differential folded cascode CMOS OP amp is combined with an adaptive bias OTA to increase the slew rate, and a continuous-time CMFB circuit with a push-pull type combination of a NMOS input and a PMOS input differential amplifiers is used to maximize the output voltage swing. The fabricated OP amp using a 0.8 µm digital CMOS process gives more than three times improvement in slew rate with a 15% increase in DC power consumption and a 7.5% increase in chip area compared to the conventional OP amp fabricated on the same die. The output voltage swing was measured to be -0.75 V -0.7 V at the supply voltage of +/-1.2 V.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e80-c_9_1203/_p

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@ARTICLE{e80-c_9_1203,
author={Jae-Yoon SIM, Cheol-Hee LEE, Won-Chang JEONG, Hong-June PARK, },
journal={IEICE TRANSACTIONS on Electronics},
title={Adaptive Biasing Folded Cascode CMOS OP Amp with Continuous-Time Push-Pull CMFB Scheme},
year={1997},
volume={E80-C},
number={9},
pages={1203-1210},
abstract={A fully differential folded cascode CMOS OP amp is combined with an adaptive bias OTA to increase the slew rate, and a continuous-time CMFB circuit with a push-pull type combination of a NMOS input and a PMOS input differential amplifiers is used to maximize the output voltage swing. The fabricated OP amp using a 0.8 µm digital CMOS process gives more than three times improvement in slew rate with a 15% increase in DC power consumption and a 7.5% increase in chip area compared to the conventional OP amp fabricated on the same die. The output voltage swing was measured to be -0.75 V -0.7 V at the supply voltage of +/-1.2 V.},
keywords={},
doi={},
ISSN={},
month={September},}

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TY - JOUR
TI - Adaptive Biasing Folded Cascode CMOS OP Amp with Continuous-Time Push-Pull CMFB Scheme
T2 - IEICE TRANSACTIONS on Electronics
SP - 1203
EP - 1210
AU - Jae-Yoon SIM
AU - Cheol-Hee LEE
AU - Won-Chang JEONG
AU - Hong-June PARK
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E80-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 1997
AB - A fully differential folded cascode CMOS OP amp is combined with an adaptive bias OTA to increase the slew rate, and a continuous-time CMFB circuit with a push-pull type combination of a NMOS input and a PMOS input differential amplifiers is used to maximize the output voltage swing. The fabricated OP amp using a 0.8 µm digital CMOS process gives more than three times improvement in slew rate with a 15% increase in DC power consumption and a 7.5% increase in chip area compared to the conventional OP amp fabricated on the same die. The output voltage swing was measured to be -0.75 V -0.7 V at the supply voltage of +/-1.2 V.
ER -