A Reconfigurable Digital Signal Processor

Boon Keat TAN; Toru OGAWA; Ryuji YOSHIMURA; Kenji TANIGUCHI

A Reconfigurable Digital Signal Processor

Boon Keat TAN, Toru OGAWA, Ryuji YOSHIMURA, Kenji TANIGUCHI

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This paper describes a new architecture-based DSP processor, which consists of n n mesh multiprocessor for digital signal processing. A prototype chip, RCDSP9701 has been designed and implemented using a CMOS 0. 6 µm process. This architecture has better performance compare to the traditional microprocessor solution to Digital Signal Processing. The proposed method poses remarkable flexibility compare to ASIC (Application Specified Integrated Circuits) approach for Digital Signal Processing applications. In addition, the proposed architecture is fault tolerant and suitable for parallel computing applications. In this paper, an implementation into a silicon chip of the new architecture is presented to give a better understanding of our work.

Publication: IEICE TRANSACTIONS on Electronics Vol.E81-C No.9 pp.1424-1430

Publication Date: 1998/09/25

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Type of Manuscript: Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)

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Boon Keat TAN, Toru OGAWA, Ryuji YOSHIMURA, Kenji TANIGUCHI, "A Reconfigurable Digital Signal Processor" in IEICE TRANSACTIONS on Electronics, vol. E81-C, no. 9, pp. 1424-1430, September 1998, doi: .
Abstract: This paper describes a new architecture-based DSP processor, which consists of n n mesh multiprocessor for digital signal processing. A prototype chip, RCDSP9701 has been designed and implemented using a CMOS 0. 6 µm process. This architecture has better performance compare to the traditional microprocessor solution to Digital Signal Processing. The proposed method poses remarkable flexibility compare to ASIC (Application Specified Integrated Circuits) approach for Digital Signal Processing applications. In addition, the proposed architecture is fault tolerant and suitable for parallel computing applications. In this paper, an implementation into a silicon chip of the new architecture is presented to give a better understanding of our work.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e81-c_9_1424/_p

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@ARTICLE{e81-c_9_1424,
author={Boon Keat TAN, Toru OGAWA, Ryuji YOSHIMURA, Kenji TANIGUCHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Reconfigurable Digital Signal Processor},
year={1998},
volume={E81-C},
number={9},
pages={1424-1430},
abstract={This paper describes a new architecture-based DSP processor, which consists of n n mesh multiprocessor for digital signal processing. A prototype chip, RCDSP9701 has been designed and implemented using a CMOS 0. 6 µm process. This architecture has better performance compare to the traditional microprocessor solution to Digital Signal Processing. The proposed method poses remarkable flexibility compare to ASIC (Application Specified Integrated Circuits) approach for Digital Signal Processing applications. In addition, the proposed architecture is fault tolerant and suitable for parallel computing applications. In this paper, an implementation into a silicon chip of the new architecture is presented to give a better understanding of our work.},
keywords={},
doi={},
ISSN={},
month={September},}

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TY - JOUR
TI - A Reconfigurable Digital Signal Processor
T2 - IEICE TRANSACTIONS on Electronics
SP - 1424
EP - 1430
AU - Boon Keat TAN
AU - Toru OGAWA
AU - Ryuji YOSHIMURA
AU - Kenji TANIGUCHI
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E81-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 1998
AB - This paper describes a new architecture-based DSP processor, which consists of n n mesh multiprocessor for digital signal processing. A prototype chip, RCDSP9701 has been designed and implemented using a CMOS 0. 6 µm process. This architecture has better performance compare to the traditional microprocessor solution to Digital Signal Processing. The proposed method poses remarkable flexibility compare to ASIC (Application Specified Integrated Circuits) approach for Digital Signal Processing applications. In addition, the proposed architecture is fault tolerant and suitable for parallel computing applications. In this paper, an implementation into a silicon chip of the new architecture is presented to give a better understanding of our work.
ER -