A new CMOS sense-amplifier type flip-flop (SAFF) is proposed. By reducing the discharging time and the loading condition, the setup/hold time is improved by 22%, the input data to clock skew by 46% and the clock to output delay by 4.4%.
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Seong-Ik CHO, Jin-Seok HEO, Hong-June PARK, Mu-Hun PARK, Young-Hee KIM, "CMOS Sense-Amplifier Type Flip-Flop Having Improved Setup/Hold Margin" in IEICE TRANSACTIONS on Electronics,
vol. E86-C, no. 12, pp. 2508-2510, December 2003, doi: .
Abstract: A new CMOS sense-amplifier type flip-flop (SAFF) is proposed. By reducing the discharging time and the loading condition, the setup/hold time is improved by 22%, the input data to clock skew by 46% and the clock to output delay by 4.4%.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e86-c_12_2508/_p
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@ARTICLE{e86-c_12_2508,
author={Seong-Ik CHO, Jin-Seok HEO, Hong-June PARK, Mu-Hun PARK, Young-Hee KIM, },
journal={IEICE TRANSACTIONS on Electronics},
title={CMOS Sense-Amplifier Type Flip-Flop Having Improved Setup/Hold Margin},
year={2003},
volume={E86-C},
number={12},
pages={2508-2510},
abstract={A new CMOS sense-amplifier type flip-flop (SAFF) is proposed. By reducing the discharging time and the loading condition, the setup/hold time is improved by 22%, the input data to clock skew by 46% and the clock to output delay by 4.4%.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - CMOS Sense-Amplifier Type Flip-Flop Having Improved Setup/Hold Margin
T2 - IEICE TRANSACTIONS on Electronics
SP - 2508
EP - 2510
AU - Seong-Ik CHO
AU - Jin-Seok HEO
AU - Hong-June PARK
AU - Mu-Hun PARK
AU - Young-Hee KIM
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E86-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2003
AB - A new CMOS sense-amplifier type flip-flop (SAFF) is proposed. By reducing the discharging time and the loading condition, the setup/hold time is improved by 22%, the input data to clock skew by 46% and the clock to output delay by 4.4%.
ER -