A Low Standby Current DSP Core Using Improved ABC-MT-CMOS with Charge Pump Circuit

Hiromi NOTANI; Masayuki KOYAMA; Ryuji MANO; Hiroshi MAKINO; Yoshio MATSUDA; Osamu TOMISAWA; Shuhei IWADE

A Low Standby Current DSP Core Using Improved ABC-MT-CMOS with Charge Pump Circuit

Hiromi NOTANI, Masayuki KOYAMA, Ryuji MANO, Hiroshi MAKINO, Yoshio MATSUDA, Osamu TOMISAWA, Shuhei IWADE

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A 64-bit 100-MHz multimedia DSP core has been designed using 0.15-µ m CMOS technology. An improved Auto-Backgate-Controlled MT-CMOS (ABC-MT-CMOS) circuit with a charge pump is adopted to suppress the standby leakage current. The dynamic active current of whole chip was simulated to optimize the size of a switch for a power supply control. The DSP core chip, which integrates 300-kgate Logic, 64-kbyte SRAM and charge pump circuit, has 8-µ A standby leakage current. The reduction rate is 1/250.

Publication: IEICE TRANSACTIONS on Electronics Vol.E86-C No.4 pp.597-603

Publication Date: 2003/04/01

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Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)

Category: Circuit Design

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Hiromi NOTANI, Masayuki KOYAMA, Ryuji MANO, Hiroshi MAKINO, Yoshio MATSUDA, Osamu TOMISAWA, Shuhei IWADE, "A Low Standby Current DSP Core Using Improved ABC-MT-CMOS with Charge Pump Circuit" in IEICE TRANSACTIONS on Electronics, vol. E86-C, no. 4, pp. 597-603, April 2003, doi: .
Abstract: A 64-bit 100-MHz multimedia DSP core has been designed using 0.15-µ m CMOS technology. An improved Auto-Backgate-Controlled MT-CMOS (ABC-MT-CMOS) circuit with a charge pump is adopted to suppress the standby leakage current. The dynamic active current of whole chip was simulated to optimize the size of a switch for a power supply control. The DSP core chip, which integrates 300-kgate Logic, 64-kbyte SRAM and charge pump circuit, has 8-µ A standby leakage current. The reduction rate is 1/250.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e86-c_4_597/_p

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@ARTICLE{e86-c_4_597,
author={Hiromi NOTANI, Masayuki KOYAMA, Ryuji MANO, Hiroshi MAKINO, Yoshio MATSUDA, Osamu TOMISAWA, Shuhei IWADE, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low Standby Current DSP Core Using Improved ABC-MT-CMOS with Charge Pump Circuit},
year={2003},
volume={E86-C},
number={4},
pages={597-603},
abstract={A 64-bit 100-MHz multimedia DSP core has been designed using 0.15-µ m CMOS technology. An improved Auto-Backgate-Controlled MT-CMOS (ABC-MT-CMOS) circuit with a charge pump is adopted to suppress the standby leakage current. The dynamic active current of whole chip was simulated to optimize the size of a switch for a power supply control. The DSP core chip, which integrates 300-kgate Logic, 64-kbyte SRAM and charge pump circuit, has 8-µ A standby leakage current. The reduction rate is 1/250.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - A Low Standby Current DSP Core Using Improved ABC-MT-CMOS with Charge Pump Circuit
T2 - IEICE TRANSACTIONS on Electronics
SP - 597
EP - 603
AU - Hiromi NOTANI
AU - Masayuki KOYAMA
AU - Ryuji MANO
AU - Hiroshi MAKINO
AU - Yoshio MATSUDA
AU - Osamu TOMISAWA
AU - Shuhei IWADE
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E86-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2003
AB - A 64-bit 100-MHz multimedia DSP core has been designed using 0.15-µ m CMOS technology. An improved Auto-Backgate-Controlled MT-CMOS (ABC-MT-CMOS) circuit with a charge pump is adopted to suppress the standby leakage current. The dynamic active current of whole chip was simulated to optimize the size of a switch for a power supply control. The DSP core chip, which integrates 300-kgate Logic, 64-kbyte SRAM and charge pump circuit, has 8-µ A standby leakage current. The reduction rate is 1/250.
ER -