Multiple Programming Method and Circuitry for a Phase Change Nonvolatile Random Access Memory (PRAM)

Masashi TAKATA; Kazuya NAKAYAMA; Toshihiko KASAI; Akio KITAGAWA

Multiple Programming Method and Circuitry for a Phase Change Nonvolatile Random Access Memory (PRAM)

Masashi TAKATA, Kazuya NAKAYAMA, Toshihiko KASAI, Akio KITAGAWA

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A novel multiple programming method for a phase change nonvolatile random access memory (NVRAM) is proposed. The resistance of the chalcogenide semiconductors (phase change materials, e.g. SeSbTe) stacked on the memory cell is controlled by the number of the applied current pulses, and we have observed experimentally 4-valued resistance in the range of 42 k-2.1kΩ at the SeSbTe discrete memory cell. On the basis of this experimental results, the 4-valued memory circuit was designed with CMOS 0.35 µm process. It has been confirmed with a circuit simulation that the multi-bit read circuit proposed works successfully under a read cycle operation over 100 MHz at 3.3 V supply voltage and the read operation is completed within 3 nsec.

Publication: IEICE TRANSACTIONS on Electronics Vol.E87-C No.10 pp.1679-1685

Publication Date: 2004/10/01

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Type of Manuscript: Special Section PAPER (Special Section on New Era of Nonvolatile Memories)

Category: Phase Change RAM

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Masashi TAKATA, Kazuya NAKAYAMA, Toshihiko KASAI, Akio KITAGAWA, "Multiple Programming Method and Circuitry for a Phase Change Nonvolatile Random Access Memory (PRAM)" in IEICE TRANSACTIONS on Electronics, vol. E87-C, no. 10, pp. 1679-1685, October 2004, doi: .
Abstract: A novel multiple programming method for a phase change nonvolatile random access memory (NVRAM) is proposed. The resistance of the chalcogenide semiconductors (phase change materials, e.g. SeSbTe) stacked on the memory cell is controlled by the number of the applied current pulses, and we have observed experimentally 4-valued resistance in the range of 42 k-2.1kΩ at the SeSbTe discrete memory cell. On the basis of this experimental results, the 4-valued memory circuit was designed with CMOS 0.35 µm process. It has been confirmed with a circuit simulation that the multi-bit read circuit proposed works successfully under a read cycle operation over 100 MHz at 3.3 V supply voltage and the read operation is completed within 3 nsec.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e87-c_10_1679/_p

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@ARTICLE{e87-c_10_1679,
author={Masashi TAKATA, Kazuya NAKAYAMA, Toshihiko KASAI, Akio KITAGAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Multiple Programming Method and Circuitry for a Phase Change Nonvolatile Random Access Memory (PRAM)},
year={2004},
volume={E87-C},
number={10},
pages={1679-1685},
abstract={A novel multiple programming method for a phase change nonvolatile random access memory (NVRAM) is proposed. The resistance of the chalcogenide semiconductors (phase change materials, e.g. SeSbTe) stacked on the memory cell is controlled by the number of the applied current pulses, and we have observed experimentally 4-valued resistance in the range of 42 k-2.1kΩ at the SeSbTe discrete memory cell. On the basis of this experimental results, the 4-valued memory circuit was designed with CMOS 0.35 µm process. It has been confirmed with a circuit simulation that the multi-bit read circuit proposed works successfully under a read cycle operation over 100 MHz at 3.3 V supply voltage and the read operation is completed within 3 nsec.},
keywords={},
doi={},
ISSN={},
month={October},}

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TY - JOUR
TI - Multiple Programming Method and Circuitry for a Phase Change Nonvolatile Random Access Memory (PRAM)
T2 - IEICE TRANSACTIONS on Electronics
SP - 1679
EP - 1685
AU - Masashi TAKATA
AU - Kazuya NAKAYAMA
AU - Toshihiko KASAI
AU - Akio KITAGAWA
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2004
AB - A novel multiple programming method for a phase change nonvolatile random access memory (NVRAM) is proposed. The resistance of the chalcogenide semiconductors (phase change materials, e.g. SeSbTe) stacked on the memory cell is controlled by the number of the applied current pulses, and we have observed experimentally 4-valued resistance in the range of 42 k-2.1kΩ at the SeSbTe discrete memory cell. On the basis of this experimental results, the 4-valued memory circuit was designed with CMOS 0.35 µm process. It has been confirmed with a circuit simulation that the multi-bit read circuit proposed works successfully under a read cycle operation over 100 MHz at 3.3 V supply voltage and the read operation is completed within 3 nsec.
ER -