This paper reviews process, device and circuit technologies of high-density flash memories, whose market has grown explosively as bridge media. In this memory, programming throughput as well as low bit costs is critical issue. To meet the requirements, we have developed multi-level AG (Assist Gate)-AND type flash memory with small effective cell size and 10 MB/s programming throughput. We clarify three challenges to the multilevel flash memory in terms of operation method, high reliability for data retention, and high-speed multilevel programming. Future trends of high-density flash memories are also discussed.

This paper describes a 0.13 µm CMOS Logic process compatible single poly gate type non-volatile (NV) memory with a differential cell architecture, which is tailored for a rewritable FUSE (CMOS-FUSE) for System-on-a Chip (SoC). This paper features the following points; 1) firstly quantified how much important is avoiding any additional process cost and area penalty rather than reducing the area of memory cell itself from the chip cost point of view for the new SoC applications. CMOS FUSE can provide cost-competitive than the high-density NV memories (50-fold higher density with 20% additional cost relative to CMOS FUSE) in the capacity range of 200 kbit for the SoC occupied the logic area of 40 mm². 2) firstly discussed in detail how much the differential cell architecture can change a data retention characteristics including an activation energy (Ea), failure-rate, and tail-bits issues relative to the conventional one based on the measured data of 0.13 µm devices. Based on the measured data retention characteristics at 300, 250, and 200, it is found that the proposed differential approach makes it possible to increase Ea by 1.5 times (from 1.52 eV to 2.23 eV), which means it can be expected to realize a 20000-fold longer data retention characteristics at 105. Even if considering the tail-bit issues for mass-production, an over 700-fold longer data retention characteristics at 105 can be expected while keeping the same failure rate (0.01 ppm) relative to the conventional OR-logical architecture. No significant V_t shifts ( 140 mV and 200 mV) were observed even after applying surge stress of +2200 V from I/O pad and 1000-times cycling of write and erase operations, respectively. In addition, 1024-bit CMOS-FUSE module has been embedded in the SoC without any additional area penalty by being laid out just beneath the power ring for SRAM macro and the stable memory read operation was verified at VDD=1.0 V under a severe I/O switching noise and an unstable VDD/GND condition in the power up sequence.

We have integrated a phase change random access memory (PRAM), completely based on 0.24 µm-CMOS technologies using nitrogen doped GeSbTe films. The Ge₂Sb₂Te₅ (GST) thin films are well known to play a critical role in writing current of PRAM. Through device simulation, we found that high-resistive GST is indispensable to minimize the writing current of PRAM. For the first time, we found the resistivity of GST film can be controlled with nitrogen doping. Doping nitrogen to GST film successfully reduced writing current. A 0.24 µm PRAM using N-doped GST films were demonstrated with writing pulse of 0.8 mA-50 ns for RESET and 0.4 mA-100 ns for SET. Also, the cell endurance has been enhanced with grain growth suppression effect of dopant nitrogen. Endurance performance of fully integrated PRAM using N-doped GST shows no fail bit up to 2E9 cycles. Allowing 1% failures, extrapolation to 85 indicates retention time of 2 years. All the results show that PRAM is one of the most promising candidates in the market for the next generation memories.

A novel multiple programming method for a phase change nonvolatile random access memory (NVRAM) is proposed. The resistance of the chalcogenide semiconductors (phase change materials, e.g. SeSbTe) stacked on the memory cell is controlled by the number of the applied current pulses, and we have observed experimentally 4-valued resistance in the range of 42 k-2.1kΩ at the SeSbTe discrete memory cell. On the basis of this experimental results, the 4-valued memory circuit was designed with CMOS 0.35 µm process. It has been confirmed with a circuit simulation that the multi-bit read circuit proposed works successfully under a read cycle operation over 100 MHz at 3.3 V supply voltage and the read operation is completed within 3 nsec.

This paper proposes a new FeRAM design style based on grounded-plate PMOS-gate (GPPG) cell structure. A GPPG cell consists of a PMOS access transistor and a ferroelectric capacitor. Its plate is grounded. The proposed scheme employs three novel operating methods: 1) V_DD precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the on-pitch plate control circuitry, it is effective in realizing cost-effective chip sizes. Implementation of a 2.5-V, 2-Mb FeRAM prototype design in a 0.5-µm technology shows a cell array efficiency of 57%, an access time of 85 ns and an active current of 12 mA, respectively.

We have fabricated ferroelectric Pb(Zr,Ti)O₃ (PZT) thin films using low-pressure consolidation process during the sol-gel method. Drastic improvements of electrical properties have been obtained for the PZT thin films fabricated with low-pressure consolidation process. A remanent polarization (P_r) of 37 µC/cm² and a coercive field (E_C) of 64 kV/cm have been achieved. In addition, the leakage current of the PZT films fabricated using low-pressure consolidation is 10² times smaller than that of the films fabricated with the usual process of sol-gel method. It is also found that the low-pressure consolidation process is effective on improvements of electrical properties of PZT films fabricated at lower crystallization temperatures and with sub-100 nm thickness.

A novel ferroelectric-gate transistor with split-gate structure has been proposed and its read out characteristics have been analyzed. "Transistor-type" FeRAMs have a problem in degradation of readout current, i.e. when the readout voltage is applied at the gate, the current of readout operation is smaller than that of write operation. We demonstrate by SPICE simulation that the proposed split-gate structure ferroelectric-FET can overcome the problem.

Identification of targets using sequential high range-resolution (HRR) radar signatures is studied. Classifiers are designed by using hidden Markov models (HMMs) to characterize the sequential information in multi-aspect HRR signatures. The higher-order moments together with the target dimension and the number of dominant wavefronts are used as features of the transient HRR waveforms. Classification results are presented for the ten-target MSTAR data set. The example results show that good classification performance and robustness are obtained, although the target features used here are very simple and compact compared with the complex HRR signatures.

A bandpass filter (BPF) with shielded inverted microstrip lines (SIMSL), previously demonstrated by the author, has shown the nontrivial asymmetry of filter responses in spite of adopting a conventional filter synthesis procedure. This paper will reveal the mechanism of the asymmetry and propose prescriptions for recovering the defect, in addition to observing the wave propagation property of SIMSL. Firstly, the behavior of phase constants or effective dielectric constants for various modes propagating on single SIMSL are indicated in terms of the line configuration, and the dispersion characteristics of the quasi-TEM mode are interpreted from the point of mode coupling between the pure TEM mode and dielectric slab modes. Then it is shown that the asymmetry is dependent only on the transmission characteristics of SIMSL parallel-coupled lines involved in the filter circuits. Theoretical considerations reveal that the asymmetry is due to the fact that SIMSL has quite different phase constants for the even- and odd-mode. On the basis of these results, the optimized BPF is designed and it is experimentally demonstrated that the symmetry of its responses is notably recovered. Furthermore, this optimization is still quite efficient for achieving high attenuation properties at its harmonics.

This paper presents a voltage-mode WTA/MAX circuit that achieves high-speed and multi-chip features. Based on the efficient averaged-value comparison approach, the time and hardware complexities are proportional to O(log N) and O(N) respectively, where N is the number of inputs. In addition, a voltage comparison element (VCE) circuit is proposed to achieve multi-chip function. In the proposed circuit, the averaged-value calculator is built using resistor array that prevents the matching problem of transistor array. The whole circuit was fabricated with the TSMC 0.35 µm signal-poly quadruple-metal CMOS process. With eight input signals, the measurement results show that the proposed circuit resolved input voltages differing by 10 mV in 30 ns, and the multi-chip capability was also verified.

A large-swing, high-driving, low-power, class-AB buffer amplifier, which consists of a high-gain input stage and a unity-gain class-AB output stage, with low variation of quiescent current is proposed. The low power consumption and low variation of the quiescent output current are achieved by using a weak-driving and a strong-driving pseudo-source followers. The high-driving capability is mainly provided by the strong-driving pseudo-source follower whose output transistors are turned off in the vicinity of the stable state to reduce the power consumption and the variation of output current, while the quiescent state is maintained by the weak-driving pseudo-source follower. The error amplifiers with source-coupled pairs of the same type transistors are merged into a single error amplifier to reduce the area of the buffer and the current consumption. An experimental prototype buffer amplifier implemented in a 0.35-µm CMOS technology demonstrates that the circuit dissipates an average static power consumption of only 388.7 µW with the standard deviation of only 3.4 µW, which is only 0.874% at a power supply of 3.3 V, and exhibits the slew rates of 2.18 V/µs and 2.50 V/µs for the rising and falling edges, respectively, under a 300 Ω /150 pF load. Both of the second and third harmonic distortions (HD2 and HD3) are -69 dB at 20 kHz under the same load.

This investigation proposes a novel dual-mode patch bandpass filter (BPF) that uses defect ground structure (DGS) to suppress spurious response. The proposed dual-mode patch BPF has exhibits a wide stopband characteristic owing to that uses the bandgap resonant characteristic of DGS in the harmonic frequency of the dual-mode patch BPF. The novel proposed filter demonstrates the frequency characteristics with center frequency f₀ = 2.2 GHz, 3-dB bandwidth (FBW) of 8% and wider stopband from 2.6 to 6 GHz at the level of -35 dB. The experimental and simulated results agree.

In this paper, a novel CMOS defuzzification circuit using dual-output current conveyors (DO-CCII) is introduced. The behaviour of the proposed circuit has been verified with PSPICE using the models for 1.2 µm MIETEC CMOS process. The proposed circuit offers high-speed operation and high accuracy because of using second generation current conveyors (CCII). The designed circuit is suitable for fuzzy logic controllers using center of gravity (COG) defuzzification method.