Design and Application of Ferroelectric Memory Based Nonvolatile SRAM

Shoichi MASUI; Tsuzumi NINOMIYA; Takashi OHKAWA; Michiya OURA; Yoshimasa HORII; Nobuhiro KIN; Koichiro HONDA

Design and Application of Ferroelectric Memory Based Nonvolatile SRAM

Shoichi MASUI, Tsuzumi NINOMIYA, Takashi OHKAWA, Michiya OURA, Yoshimasa HORII, Nobuhiro KIN, Koichiro HONDA

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Circuit techniques to realize stable recall operation and virtually unlimited read/program cycle operations in ferroelectric memory based nonvolatile (NV) SRAM composed of six-transistor and four-ferroelectric capacitor cells have been developed. Unlimited program cycle operation independent of ferroelectric material characteristics is realized by proper control of plate lines. Reliability evaluation results show that the developed memory cell has sufficient operation margin after stresses of temperature, fatigue, DC bias. Application of NV-SRAM to programmable logic devices has been discussed with a prototype of dynamically programmable gate arrays.

Publication: IEICE TRANSACTIONS on Electronics Vol.E87-C No.11 pp.1769-1776

Publication Date: 2004/11/01

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Type of Manuscript: Special Section INVITED PAPER (Special Section on New System Paradigms for Integrated Electronics)

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Shoichi MASUI, Tsuzumi NINOMIYA, Takashi OHKAWA, Michiya OURA, Yoshimasa HORII, Nobuhiro KIN, Koichiro HONDA, "Design and Application of Ferroelectric Memory Based Nonvolatile SRAM" in IEICE TRANSACTIONS on Electronics, vol. E87-C, no. 11, pp. 1769-1776, November 2004, doi: .
Abstract: Circuit techniques to realize stable recall operation and virtually unlimited read/program cycle operations in ferroelectric memory based nonvolatile (NV) SRAM composed of six-transistor and four-ferroelectric capacitor cells have been developed. Unlimited program cycle operation independent of ferroelectric material characteristics is realized by proper control of plate lines. Reliability evaluation results show that the developed memory cell has sufficient operation margin after stresses of temperature, fatigue, DC bias. Application of NV-SRAM to programmable logic devices has been discussed with a prototype of dynamically programmable gate arrays.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e87-c_11_1769/_p

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@ARTICLE{e87-c_11_1769,
author={Shoichi MASUI, Tsuzumi NINOMIYA, Takashi OHKAWA, Michiya OURA, Yoshimasa HORII, Nobuhiro KIN, Koichiro HONDA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design and Application of Ferroelectric Memory Based Nonvolatile SRAM},
year={2004},
volume={E87-C},
number={11},
pages={1769-1776},
abstract={Circuit techniques to realize stable recall operation and virtually unlimited read/program cycle operations in ferroelectric memory based nonvolatile (NV) SRAM composed of six-transistor and four-ferroelectric capacitor cells have been developed. Unlimited program cycle operation independent of ferroelectric material characteristics is realized by proper control of plate lines. Reliability evaluation results show that the developed memory cell has sufficient operation margin after stresses of temperature, fatigue, DC bias. Application of NV-SRAM to programmable logic devices has been discussed with a prototype of dynamically programmable gate arrays.},
keywords={},
doi={},
ISSN={},
month={November},}

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TY - JOUR
TI - Design and Application of Ferroelectric Memory Based Nonvolatile SRAM
T2 - IEICE TRANSACTIONS on Electronics
SP - 1769
EP - 1776
AU - Shoichi MASUI
AU - Tsuzumi NINOMIYA
AU - Takashi OHKAWA
AU - Michiya OURA
AU - Yoshimasa HORII
AU - Nobuhiro KIN
AU - Koichiro HONDA
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2004
AB - Circuit techniques to realize stable recall operation and virtually unlimited read/program cycle operations in ferroelectric memory based nonvolatile (NV) SRAM composed of six-transistor and four-ferroelectric capacitor cells have been developed. Unlimited program cycle operation independent of ferroelectric material characteristics is realized by proper control of plate lines. Reliability evaluation results show that the developed memory cell has sufficient operation margin after stresses of temperature, fatigue, DC bias. Application of NV-SRAM to programmable logic devices has been discussed with a prototype of dynamically programmable gate arrays.
ER -