A Wide Range 1.0-3.6 V 200 Mbps, Push-Pull Output Buffer Using Parasitic Bipolar Transistors

Takahiro SHIMADA; Hiromi NOTANI; Yasunobu NAKASE; Hiroshi MAKINO; Shuhei IWADE

A Wide Range 1.0-3.6 V 200 Mbps, Push-Pull Output Buffer Using Parasitic Bipolar Transistors

Takahiro SHIMADA, Hiromi NOTANI, Yasunobu NAKASE, Hiroshi MAKINO, Shuhei IWADE

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We proposed a push-pull output buffer that maintains the data transmission rate for lower supply voltages. It operates at an internal supply voltage (VDD) of 0.7-1.6 V and an interface supply voltage (VDDX) of 1.0-3.6 V. In low VDDX operation, the output buffer utilizes parasitic bipolar transistors instead of MOS transistors to maintain drivability. Furthermore forward body bias (FBB) control is provided for the level converter in low VDD operation. We fabricated a test chip with a standard 0.15 µm CMOS process. Measurement results indicate that the proposed output buffer achieves 200 Mbps operation at VDD of 0.7 V and VDDX of 1.0 V.

Publication: IEICE TRANSACTIONS on Electronics Vol.E87-C No.4 pp.571-577

Publication Date: 2004/04/01

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Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)

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Takahiro SHIMADA, Hiromi NOTANI, Yasunobu NAKASE, Hiroshi MAKINO, Shuhei IWADE, "A Wide Range 1.0-3.6 V 200 Mbps, Push-Pull Output Buffer Using Parasitic Bipolar Transistors" in IEICE TRANSACTIONS on Electronics, vol. E87-C, no. 4, pp. 571-577, April 2004, doi: .
Abstract: We proposed a push-pull output buffer that maintains the data transmission rate for lower supply voltages. It operates at an internal supply voltage (VDD) of 0.7-1.6 V and an interface supply voltage (VDDX) of 1.0-3.6 V. In low VDDX operation, the output buffer utilizes parasitic bipolar transistors instead of MOS transistors to maintain drivability. Furthermore forward body bias (FBB) control is provided for the level converter in low VDD operation. We fabricated a test chip with a standard 0.15 µm CMOS process. Measurement results indicate that the proposed output buffer achieves 200 Mbps operation at VDD of 0.7 V and VDDX of 1.0 V.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e87-c_4_571/_p

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@ARTICLE{e87-c_4_571,
author={Takahiro SHIMADA, Hiromi NOTANI, Yasunobu NAKASE, Hiroshi MAKINO, Shuhei IWADE, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Wide Range 1.0-3.6 V 200 Mbps, Push-Pull Output Buffer Using Parasitic Bipolar Transistors},
year={2004},
volume={E87-C},
number={4},
pages={571-577},
abstract={We proposed a push-pull output buffer that maintains the data transmission rate for lower supply voltages. It operates at an internal supply voltage (VDD) of 0.7-1.6 V and an interface supply voltage (VDDX) of 1.0-3.6 V. In low VDDX operation, the output buffer utilizes parasitic bipolar transistors instead of MOS transistors to maintain drivability. Furthermore forward body bias (FBB) control is provided for the level converter in low VDD operation. We fabricated a test chip with a standard 0.15 µm CMOS process. Measurement results indicate that the proposed output buffer achieves 200 Mbps operation at VDD of 0.7 V and VDDX of 1.0 V.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - A Wide Range 1.0-3.6 V 200 Mbps, Push-Pull Output Buffer Using Parasitic Bipolar Transistors
T2 - IEICE TRANSACTIONS on Electronics
SP - 571
EP - 577
AU - Takahiro SHIMADA
AU - Hiromi NOTANI
AU - Yasunobu NAKASE
AU - Hiroshi MAKINO
AU - Shuhei IWADE
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2004
AB - We proposed a push-pull output buffer that maintains the data transmission rate for lower supply voltages. It operates at an internal supply voltage (VDD) of 0.7-1.6 V and an interface supply voltage (VDDX) of 1.0-3.6 V. In low VDDX operation, the output buffer utilizes parasitic bipolar transistors instead of MOS transistors to maintain drivability. Furthermore forward body bias (FBB) control is provided for the level converter in low VDD operation. We fabricated a test chip with a standard 0.15 µm CMOS process. Measurement results indicate that the proposed output buffer achieves 200 Mbps operation at VDD of 0.7 V and VDDX of 1.0 V.
ER -