A Time-Interleaved Switched-Capacitor Band-Pass Delta-Sigma Modulator with Recursive Loop

Minho KWON; Jungyoon LEE; Gunhee HAN

A Time-Interleaved Switched-Capacitor Band-Pass Delta-Sigma Modulator with Recursive Loop

Minho KWON, Jungyoon LEE, Gunhee HAN

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A band-pass delta-sigma modulator (BPDSM) is a key building block to implement a digital intermediate frequency (IF) receiver in a wireless communication system. This paper proposes a time-interleaved (TI) switched-capacitor (SC) BPDSM architecture that consists of 5-stage TI blocks with recursive loop. The proposed TI BPDSM provides reduction in the clock frequency requirement by a factor of 5 and relaxes the settling time requirement to one-fourth of conventional approach. The test chip was designed and fabricated for a 30-MHz IF system with a 0.35-µm CMOS process. The measured peak SNR for a 200-kHz bandwidth is 63 dB while dissipating 75 mW from a 3.3-V supply and occupying 1.3 mm².

Publication: IEICE TRANSACTIONS on Electronics Vol.E87-C No.5 pp.785-790

Publication Date: 2004/05/01

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Type of Manuscript: PAPER

Category: Electronic Circuits

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Minho KWON, Jungyoon LEE, Gunhee HAN, "A Time-Interleaved Switched-Capacitor Band-Pass Delta-Sigma Modulator with Recursive Loop" in IEICE TRANSACTIONS on Electronics, vol. E87-C, no. 5, pp. 785-790, May 2004, doi: .
Abstract: A band-pass delta-sigma modulator (BPDSM) is a key building block to implement a digital intermediate frequency (IF) receiver in a wireless communication system. This paper proposes a time-interleaved (TI) switched-capacitor (SC) BPDSM architecture that consists of 5-stage TI blocks with recursive loop. The proposed TI BPDSM provides reduction in the clock frequency requirement by a factor of 5 and relaxes the settling time requirement to one-fourth of conventional approach. The test chip was designed and fabricated for a 30-MHz IF system with a 0.35-µm CMOS process. The measured peak SNR for a 200-kHz bandwidth is 63 dB while dissipating 75 mW from a 3.3-V supply and occupying 1.3 mm².
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e87-c_5_785/_p

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@ARTICLE{e87-c_5_785,
author={Minho KWON, Jungyoon LEE, Gunhee HAN, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Time-Interleaved Switched-Capacitor Band-Pass Delta-Sigma Modulator with Recursive Loop},
year={2004},
volume={E87-C},
number={5},
pages={785-790},
abstract={A band-pass delta-sigma modulator (BPDSM) is a key building block to implement a digital intermediate frequency (IF) receiver in a wireless communication system. This paper proposes a time-interleaved (TI) switched-capacitor (SC) BPDSM architecture that consists of 5-stage TI blocks with recursive loop. The proposed TI BPDSM provides reduction in the clock frequency requirement by a factor of 5 and relaxes the settling time requirement to one-fourth of conventional approach. The test chip was designed and fabricated for a 30-MHz IF system with a 0.35-µm CMOS process. The measured peak SNR for a 200-kHz bandwidth is 63 dB while dissipating 75 mW from a 3.3-V supply and occupying 1.3 mm².},
keywords={},
doi={},
ISSN={},
month={May},}

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TY - JOUR
TI - A Time-Interleaved Switched-Capacitor Band-Pass Delta-Sigma Modulator with Recursive Loop
T2 - IEICE TRANSACTIONS on Electronics
SP - 785
EP - 790
AU - Minho KWON
AU - Jungyoon LEE
AU - Gunhee HAN
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2004
AB - A band-pass delta-sigma modulator (BPDSM) is a key building block to implement a digital intermediate frequency (IF) receiver in a wireless communication system. This paper proposes a time-interleaved (TI) switched-capacitor (SC) BPDSM architecture that consists of 5-stage TI blocks with recursive loop. The proposed TI BPDSM provides reduction in the clock frequency requirement by a factor of 5 and relaxes the settling time requirement to one-fourth of conventional approach. The test chip was designed and fabricated for a 30-MHz IF system with a 0.35-µm CMOS process. The measured peak SNR for a 200-kHz bandwidth is 63 dB while dissipating 75 mW from a 3.3-V supply and occupying 1.3 mm².
ER -