DOA (Direction Of Arrival) estimation is a useful technique in various positioning applications including the DOA-based adaptive array antenna system. This paper presents a practical implementation of FPGA (Field Programmable Gate Array) based fast DOA estimator for wireless cellular basestation. This system incorporates spectral unitary MUSIC (MUltiple SIgnal Classification) algorithm, which is one of the representative super resolution DOA estimation techniques. This paper proposes a way of digital signal processor design suitable for FPGA and its real hardware implementation. In this system, all digital signal processing procedures are computed by the only fixed-point operation with finite word-length for fast processing and low power consumption. The performance will be assessed by hardware level simulations and experiments in a radio anechoic chamber.
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Minseok KIM, Koichi ICHIGE, Hiroyuki ARAI, "Implementation of FPGA Based Fast Unitary MUSIC DOA Estimator" in IEICE TRANSACTIONS on Electronics,
vol. E87-C, no. 9, pp. 1485-1494, September 2004, doi: .
Abstract: DOA (Direction Of Arrival) estimation is a useful technique in various positioning applications including the DOA-based adaptive array antenna system. This paper presents a practical implementation of FPGA (Field Programmable Gate Array) based fast DOA estimator for wireless cellular basestation. This system incorporates spectral unitary MUSIC (MUltiple SIgnal Classification) algorithm, which is one of the representative super resolution DOA estimation techniques. This paper proposes a way of digital signal processor design suitable for FPGA and its real hardware implementation. In this system, all digital signal processing procedures are computed by the only fixed-point operation with finite word-length for fast processing and low power consumption. The performance will be assessed by hardware level simulations and experiments in a radio anechoic chamber.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e87-c_9_1485/_p
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@ARTICLE{e87-c_9_1485,
author={Minseok KIM, Koichi ICHIGE, Hiroyuki ARAI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Implementation of FPGA Based Fast Unitary MUSIC DOA Estimator},
year={2004},
volume={E87-C},
number={9},
pages={1485-1494},
abstract={DOA (Direction Of Arrival) estimation is a useful technique in various positioning applications including the DOA-based adaptive array antenna system. This paper presents a practical implementation of FPGA (Field Programmable Gate Array) based fast DOA estimator for wireless cellular basestation. This system incorporates spectral unitary MUSIC (MUltiple SIgnal Classification) algorithm, which is one of the representative super resolution DOA estimation techniques. This paper proposes a way of digital signal processor design suitable for FPGA and its real hardware implementation. In this system, all digital signal processing procedures are computed by the only fixed-point operation with finite word-length for fast processing and low power consumption. The performance will be assessed by hardware level simulations and experiments in a radio anechoic chamber.},
keywords={},
doi={},
ISSN={},
month={September},}
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TY - JOUR
TI - Implementation of FPGA Based Fast Unitary MUSIC DOA Estimator
T2 - IEICE TRANSACTIONS on Electronics
SP - 1485
EP - 1494
AU - Minseok KIM
AU - Koichi ICHIGE
AU - Hiroyuki ARAI
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2004
AB - DOA (Direction Of Arrival) estimation is a useful technique in various positioning applications including the DOA-based adaptive array antenna system. This paper presents a practical implementation of FPGA (Field Programmable Gate Array) based fast DOA estimator for wireless cellular basestation. This system incorporates spectral unitary MUSIC (MUltiple SIgnal Classification) algorithm, which is one of the representative super resolution DOA estimation techniques. This paper proposes a way of digital signal processor design suitable for FPGA and its real hardware implementation. In this system, all digital signal processing procedures are computed by the only fixed-point operation with finite word-length for fast processing and low power consumption. The performance will be assessed by hardware level simulations and experiments in a radio anechoic chamber.
ER -