Wireless channel emulators are used for the performance evaluation of wireless systems when actual wireless environment test is infeasible. The main contribution of this paper is the design of a MU-MIMO channel emulator capable of sending channel feedback automatically to the access point from the generated channel coefficients after the programmable time duration. This function is used for MU beamforming features of IEEE 802.11ac. The second contribution is the low complexity design of MIMO channel emulator with a single path implementation for all MIMO channel taps. A single path design allows all elements of the MIMO channel matrix to use only one Gaussian noise generator, Doppler filter, spatial correlation channel and Rician fading emulator to minimize the hardware complexity. In addition, single path implementation allows the addition of the feedback channel output with only a few additional non-sequential elements which would otherwise double in a parallel implementation. To demonstrate the functionality of our MU-MIMO channel emulator, we present actual hardware emulator results of MU-BF receive signal constellation on oscilloscope.

Pairing-based cryptography has realized a lot of innovative cryptographic applications such as attribute-based cryptography and semi homomorphic encryption. Pairing is a bilinear map constructed on a torsion group structure that is defined on a special class of elliptic curves, namely pairing-friendly curve. Pairing-friendly curves are roughly classified into supersingular and non supersingular curves. In these years, non supersingular pairing-friendly curves have been focused on from a security reason. Although non supersingular pairing-friendly curves have an ability to bridge various security levels with various parameter settings, most of software and hardware implementations tightly restrict them to achieve calculation efficiencies and avoid implementation difficulties. This paper shows an FPGA implementation that supports various parameter settings of pairings on non supersingular pairing-friendly curves for which Montgomery reduction, cyclic vector multiplication algorithm, projective coordinates, and Tate pairing have been combinatorially applied. Then, some experimental results with resource usages are shown.

This letter presents the architecture of multi-gigabit parallel demodulator suitable for demodulating high order QAM modulated signal and easy to implement on FPGA platform. The parallel architecture is based on frequency domain implementation of matched filter and timing phase correction. Parallel FIFO based delete-keep algorithm is proposed for timing synchronization, while a kind of reduced constellation phase-frequency detector based parallel decision feedback PLL is designed for carrier synchronization. A fully pipelined parallel adaptive blind equalization algorithm is also proposed. Their parallel implementation structures suitable for FPGA platform are investigated. Besides, in the demonstration of 2 Gbps demodulator for 16QAM modulation, the architecture is implemented and validated on a Xilinx V6 FPGA platform with performance loss less than 2 dB.

Multihop network is an approach utilizing distributed wireless stations for relaying. In this system, area size, coverage and total transmit power efficiency can be improved. It is shown by computer simulations that the cooperative relaying scheme provides transmit diversity effect, and can offer much better performance compared with that of non-cooperation case. To confirm this superior performance in actual environments, field trials using real time communication equipments are now being planned. This paper reports the design and the performance of wireless equipments for field trials.

MD5 is a cryptographic algorithm used for authentication. When implemented in hardware, the performance is affected by the data dependency of the iterative compression function. In this paper, a new functional description is proposed with the aim of achieving higher throughput by mean of reducing the critical path and latency. This description can be used in similar structures of other hash algorithms, such as SHA-1, SHA-2 and RIPEMD-160, which have comparable data dependence. The proposed MD5 hardware architecture achieves a high throughput/area ratio, results of implementation in an FPGA are presented and discussed, as well as comparisons against related works.

To use the voluntary electromyogram (EMG) as a control signal of the EMG controlled functional electrical stimulator (FES), it is required to reduce the stimulation artifact and non-voluntary contribution (M-wave). In this study, a Gram-Schmidt (GS) prediction error filter (PEF) that can effectively eliminates the M-wave from voluntary EMG is presented. Also, the presented GS PEF is implemented on the field the programmable gate array (FPGA) for real-time processing and the performance is tested with simulated and real signals. Experimental results showed that GS-PEF was effective in reducing M-wave and preserving voluntary EMG.

DOA (Direction Of Arrival) estimation is a useful technique in various positioning applications including the DOA-based adaptive array antenna system. This paper presents a practical implementation of FPGA (Field Programmable Gate Array) based fast DOA estimator for wireless cellular basestation. This system incorporates spectral unitary MUSIC (MUltiple SIgnal Classification) algorithm, which is one of the representative super resolution DOA estimation techniques. This paper proposes a way of digital signal processor design suitable for FPGA and its real hardware implementation. In this system, all digital signal processing procedures are computed by the only fixed-point operation with finite word-length for fast processing and low power consumption. The performance will be assessed by hardware level simulations and experiments in a radio anechoic chamber.

Computing the Eigen Value Decomposition (EVD) of a symmetric matrix is a frequently encountered problem in adaptive (or smart or software) antenna signal processing, for example, super resolution DOA (Direction Of Arrival) estimation algorithms such as MUSIC (MUltiple SIgnal Classification) and ESPRIT (Estimation of Signal Parameters via Rotational Invariance Technique). In this paper the hardware architecture of the fast EVD processor of symmetric correlation matrices for the application of an adaptive antenna technology such as DOA estimation is proposed and the basic idea is also presented. Cyclic Jacobi method is well known for the simplest algorithm and easily implemented but its convergence time is slower than other factorization algorithm like QR-method. But if considering the fast parallel computation of the EVD with a hardware architecture like ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array), the Jacobi method can be a appropriate solution, since it offers a quite higher degree of parallelism and easier implementation than other factorization algorithms. This paper computes the EVD using a Jacobi-type method, where the vector rotations and the angles of the rotations are obtained by CORDIC (COordinate Rotation DIgital Computer). The hardware architecture suitable for ASIC or FPGA with fixed-point arithmetic is presented. Because it consists of only shift and add operations, this hardware friendly feature provides easy and efficient implementation. In this paper, the computational load, the estimate of circuit scale and expected performance are discussed and the validation of fixed-point arithmetic for the practical application to MUSIC DOA estimation is examined.

In this letter, a digital circuit realizing a Rossler model is proposed. The proposed circuit features exact reproducibility of chaos signals which is desired in chaos-based communication systems. By employing an FPGA implementation, the proposed circuit can achieve high-speed and low-cost realization. The chaotic behavior of the quasi-chaos of the proposed circuit is analyzed by numerical simulations. To confirm the validity of the FPGA implementation, the proposed circuit is designed by using an FPGA CAD tool, Verilog-HDL. This circuit design showed that the proposed circuit can be implemented onto a single FPGA and can realize real-time chaos generation.