Exploiting Sparse Activation for Low-Power Design of Synchronous Neuromorphic Systems

Jaeyong CHUNG; Woochul KANG

doi:10.1587/transele.E100.C.1073

Exploiting Sparse Activation for Low-Power Design of Synchronous Neuromorphic Systems

Jaeyong CHUNG, Woochul KANG

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Massive amounts of computation involved in real-time evaluation of deep neural networks pose a serious challenge in battery-powered systems, and neuromorphic systems specialized in neural networks have been developed. This paper first shows the portion of active neurons at a time dwindles as going toward the output layer in recent large-scale deep convolutional neural networks. Spike-based, asynchronous neuromorphic systems take advantage of the sparse activation and reduce dynamic power consumption, while synchronous systems may waste much dynamic power even for the sparse activation due to clocks. We thus propose a clock gating-based dynamic power reduction method that exploits the sparse activation for synchronous neuromorphic systems. We apply the proposed method to a building block of a recently proposed synchronous neuromorphic computing system and demonstrate up to 79% dynamic power saving at a negligible overhead.

Publication: IEICE TRANSACTIONS on Electronics Vol.E100-C No.11 pp.1073-1076

Publication Date: 2017/11/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E100.C.1073

Type of Manuscript: BRIEF PAPER

Category: Integrated Electronics

Authors

Jaeyong CHUNG
Incheon National University
Woochul KANG
Incheon National University

Keyword

neuromorphic systems, VLSI design, computer-aided design

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Jaeyong CHUNG, Woochul KANG, "Exploiting Sparse Activation for Low-Power Design of Synchronous Neuromorphic Systems" in IEICE TRANSACTIONS on Electronics, vol. E100-C, no. 11, pp. 1073-1076, November 2017, doi: 10.1587/transele.E100.C.1073.
Abstract: Massive amounts of computation involved in real-time evaluation of deep neural networks pose a serious challenge in battery-powered systems, and neuromorphic systems specialized in neural networks have been developed. This paper first shows the portion of active neurons at a time dwindles as going toward the output layer in recent large-scale deep convolutional neural networks. Spike-based, asynchronous neuromorphic systems take advantage of the sparse activation and reduce dynamic power consumption, while synchronous systems may waste much dynamic power even for the sparse activation due to clocks. We thus propose a clock gating-based dynamic power reduction method that exploits the sparse activation for synchronous neuromorphic systems. We apply the proposed method to a building block of a recently proposed synchronous neuromorphic computing system and demonstrate up to 79% dynamic power saving at a negligible overhead.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E100.C.1073/_p

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@ARTICLE{e100-c_11_1073,
author={Jaeyong CHUNG, Woochul KANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={Exploiting Sparse Activation for Low-Power Design of Synchronous Neuromorphic Systems},
year={2017},
volume={E100-C},
number={11},
pages={1073-1076},
abstract={Massive amounts of computation involved in real-time evaluation of deep neural networks pose a serious challenge in battery-powered systems, and neuromorphic systems specialized in neural networks have been developed. This paper first shows the portion of active neurons at a time dwindles as going toward the output layer in recent large-scale deep convolutional neural networks. Spike-based, asynchronous neuromorphic systems take advantage of the sparse activation and reduce dynamic power consumption, while synchronous systems may waste much dynamic power even for the sparse activation due to clocks. We thus propose a clock gating-based dynamic power reduction method that exploits the sparse activation for synchronous neuromorphic systems. We apply the proposed method to a building block of a recently proposed synchronous neuromorphic computing system and demonstrate up to 79% dynamic power saving at a negligible overhead.},
keywords={},
doi={10.1587/transele.E100.C.1073},
ISSN={1745-1353},
month={November},}

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TY - JOUR
TI - Exploiting Sparse Activation for Low-Power Design of Synchronous Neuromorphic Systems
T2 - IEICE TRANSACTIONS on Electronics
SP - 1073
EP - 1076
AU - Jaeyong CHUNG
AU - Woochul KANG
PY - 2017
DO - 10.1587/transele.E100.C.1073
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E100-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2017
AB - Massive amounts of computation involved in real-time evaluation of deep neural networks pose a serious challenge in battery-powered systems, and neuromorphic systems specialized in neural networks have been developed. This paper first shows the portion of active neurons at a time dwindles as going toward the output layer in recent large-scale deep convolutional neural networks. Spike-based, asynchronous neuromorphic systems take advantage of the sparse activation and reduce dynamic power consumption, while synchronous systems may waste much dynamic power even for the sparse activation due to clocks. We thus propose a clock gating-based dynamic power reduction method that exploits the sparse activation for synchronous neuromorphic systems. We apply the proposed method to a building block of a recently proposed synchronous neuromorphic computing system and demonstrate up to 79% dynamic power saving at a negligible overhead.
ER -