A Region-Based Through-Silicon via Repair Method for Clustered Faults

Tianming NI; Huaguo LIANG; Mu NIE; Xiumin XU; Aibin YAN; Zhengfeng HUANG

doi:10.1587/transele.E100.C.1108

A Region-Based Through-Silicon via Repair Method for Clustered Faults

Tianming NI, Huaguo LIANG, Mu NIE, Xiumin XU, Aibin YAN, Zhengfeng HUANG

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Three-dimensional integrated circuits (3D ICs) that employ through-silicon vias (TSVs) integrating multiple dies vertically have opened up the potential of highly improved circuit designs. However, various types of TSV defects may occur during the assembly process, especially the clustered TSV faults because of the winding level of thinned wafer, the surface roughness and cleanness of silicon dies,inducing TSV yield reduction greatly. To tackle this fault clustering problem, router-based and ring-based TSV redundancy architectures were previously proposed. However, these schemes either require too much area overhead or have limited reparability to tolerant clustered TSV faults. Furthermore, the repairing lengths of these schemes are too long to be ignored, leading to additional delay overhead, which may cause timing violation. In this paper, we propose a region-based TSV redundancy design to achieve relatively high reparability as well as low additional delay overhead. Simulation results show that for a given number of TSVs (8*8) and TSV failure rate (1%), our design achieves 11.27% and 20.79% reduction of delay overhead as compared with router-based design and ring-based scheme, respectively. In addition, the reparability of our proposed scheme is much better than ring-based design by 30.84%, while it is close to that of the router-based scheme. More importantly, the overall TSV yield of our design achieves 99.88%, which is slightly higher than that of both router-based method (99.53%) and ring-based design (99.00%).

Publication: IEICE TRANSACTIONS on Electronics Vol.E100-C No.12 pp.1108-1117

Publication Date: 2017/12/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E100.C.1108

Type of Manuscript: PAPER

Category: Integrated Electronics

Authors

Tianming NI
  Hefei University of Technology
Huaguo LIANG
  Hefei University of Technology
Mu NIE
  Hefei University of Technology
Xiumin XU
  Hefei University of Technology
Aibin YAN
  Anhui University
Zhengfeng HUANG
  Hefei University of Technology

Keyword

3D ICs, yield enhancement, TSV redundancy, reparability, additional delay overhead

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Tianming NI, Huaguo LIANG, Mu NIE, Xiumin XU, Aibin YAN, Zhengfeng HUANG, "A Region-Based Through-Silicon via Repair Method for Clustered Faults" in IEICE TRANSACTIONS on Electronics, vol. E100-C, no. 12, pp. 1108-1117, December 2017, doi: 10.1587/transele.E100.C.1108.
Abstract: Three-dimensional integrated circuits (3D ICs) that employ through-silicon vias (TSVs) integrating multiple dies vertically have opened up the potential of highly improved circuit designs. However, various types of TSV defects may occur during the assembly process, especially the clustered TSV faults because of the winding level of thinned wafer, the surface roughness and cleanness of silicon dies,inducing TSV yield reduction greatly. To tackle this fault clustering problem, router-based and ring-based TSV redundancy architectures were previously proposed. However, these schemes either require too much area overhead or have limited reparability to tolerant clustered TSV faults. Furthermore, the repairing lengths of these schemes are too long to be ignored, leading to additional delay overhead, which may cause timing violation. In this paper, we propose a region-based TSV redundancy design to achieve relatively high reparability as well as low additional delay overhead. Simulation results show that for a given number of TSVs (8*8) and TSV failure rate (1%), our design achieves 11.27% and 20.79% reduction of delay overhead as compared with router-based design and ring-based scheme, respectively. In addition, the reparability of our proposed scheme is much better than ring-based design by 30.84%, while it is close to that of the router-based scheme. More importantly, the overall TSV yield of our design achieves 99.88%, which is slightly higher than that of both router-based method (99.53%) and ring-based design (99.00%).
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E100.C.1108/_p

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@ARTICLE{e100-c_12_1108,
author={Tianming NI, Huaguo LIANG, Mu NIE, Xiumin XU, Aibin YAN, Zhengfeng HUANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Region-Based Through-Silicon via Repair Method for Clustered Faults},
year={2017},
volume={E100-C},
number={12},
pages={1108-1117},
abstract={Three-dimensional integrated circuits (3D ICs) that employ through-silicon vias (TSVs) integrating multiple dies vertically have opened up the potential of highly improved circuit designs. However, various types of TSV defects may occur during the assembly process, especially the clustered TSV faults because of the winding level of thinned wafer, the surface roughness and cleanness of silicon dies,inducing TSV yield reduction greatly. To tackle this fault clustering problem, router-based and ring-based TSV redundancy architectures were previously proposed. However, these schemes either require too much area overhead or have limited reparability to tolerant clustered TSV faults. Furthermore, the repairing lengths of these schemes are too long to be ignored, leading to additional delay overhead, which may cause timing violation. In this paper, we propose a region-based TSV redundancy design to achieve relatively high reparability as well as low additional delay overhead. Simulation results show that for a given number of TSVs (8*8) and TSV failure rate (1%), our design achieves 11.27% and 20.79% reduction of delay overhead as compared with router-based design and ring-based scheme, respectively. In addition, the reparability of our proposed scheme is much better than ring-based design by 30.84%, while it is close to that of the router-based scheme. More importantly, the overall TSV yield of our design achieves 99.88%, which is slightly higher than that of both router-based method (99.53%) and ring-based design (99.00%).},
keywords={},
doi={10.1587/transele.E100.C.1108},
ISSN={1745-1353},
month={December},}

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TY - JOUR
TI - A Region-Based Through-Silicon via Repair Method for Clustered Faults
T2 - IEICE TRANSACTIONS on Electronics
SP - 1108
EP - 1117
AU - Tianming NI
AU - Huaguo LIANG
AU - Mu NIE
AU - Xiumin XU
AU - Aibin YAN
AU - Zhengfeng HUANG
PY - 2017
DO - 10.1587/transele.E100.C.1108
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E100-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2017
AB - Three-dimensional integrated circuits (3D ICs) that employ through-silicon vias (TSVs) integrating multiple dies vertically have opened up the potential of highly improved circuit designs. However, various types of TSV defects may occur during the assembly process, especially the clustered TSV faults because of the winding level of thinned wafer, the surface roughness and cleanness of silicon dies,inducing TSV yield reduction greatly. To tackle this fault clustering problem, router-based and ring-based TSV redundancy architectures were previously proposed. However, these schemes either require too much area overhead or have limited reparability to tolerant clustered TSV faults. Furthermore, the repairing lengths of these schemes are too long to be ignored, leading to additional delay overhead, which may cause timing violation. In this paper, we propose a region-based TSV redundancy design to achieve relatively high reparability as well as low additional delay overhead. Simulation results show that for a given number of TSVs (8*8) and TSV failure rate (1%), our design achieves 11.27% and 20.79% reduction of delay overhead as compared with router-based design and ring-based scheme, respectively. In addition, the reparability of our proposed scheme is much better than ring-based design by 30.84%, while it is close to that of the router-based scheme. More importantly, the overall TSV yield of our design achieves 99.88%, which is slightly higher than that of both router-based method (99.53%) and ring-based design (99.00%).
ER -