A 7GS/s Complete-DDFS-Solution in 65nm CMOS

Abdel MARTINEZ ALONSO; Masaya MIYAHARA; Akira MATSUZAWA

doi:10.1587/transele.E101.C.206

A 7GS/s Complete-DDFS-Solution in 65nm CMOS

Abdel MARTINEZ ALONSO, Masaya MIYAHARA, Akira MATSUZAWA

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A 7GS/s complete-DDFS-solution featuring a two-times interleaved RDAC with 1.2Vpp-diff output swing was fabricated in 65nm CMOS. The frequency tuning and amplitude resolutions are 24-bits and 10-bits respectively. The RDAC includes a mixed-signal, high-speed architecture for random swapping thermometer coding dynamic element matching that improves the narrowband SFDR up to 8dB for output frequencies below 1.85GHz. The proposed techniques enable a 7 GS/s operation with a spurious-free dynamic range better than 32dBc over the full Nyquist bandwidth. The worst case narrowband SFDR is 42dBc. This system consumes 87.9mW/(GS/s) from a 1.2V power supply when the RSTC-DEM method is enabled, resulting in a FoM of 458.9GS/s·2^(SFDR/6)/W. A proof-of-concept chip with an active area of only 0.22mm² was measured in prototypes encapsulated in a 144-pins low profile quad flat package.

Publication: IEICE TRANSACTIONS on Electronics Vol.E101-C No.4 pp.206-217

Publication Date: 2018/04/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E101.C.206

Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)

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Authors

Abdel MARTINEZ ALONSO
  Tokyo Institute of Technology
Masaya MIYAHARA
  Tokyo Institute of Technology
Akira MATSUZAWA
  Tokyo Institute of Technology

Keyword

complete-DDFS-solution, high-speed DDFS, CMOS, RDAC, RSTC-DEM, rail-to-rail operation, two-times interleaved

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Abdel MARTINEZ ALONSO, Masaya MIYAHARA, Akira MATSUZAWA, "A 7GS/s Complete-DDFS-Solution in 65nm CMOS" in IEICE TRANSACTIONS on Electronics, vol. E101-C, no. 4, pp. 206-217, April 2018, doi: 10.1587/transele.E101.C.206.
Abstract: A 7GS/s complete-DDFS-solution featuring a two-times interleaved RDAC with 1.2Vpp-diff output swing was fabricated in 65nm CMOS. The frequency tuning and amplitude resolutions are 24-bits and 10-bits respectively. The RDAC includes a mixed-signal, high-speed architecture for random swapping thermometer coding dynamic element matching that improves the narrowband SFDR up to 8dB for output frequencies below 1.85GHz. The proposed techniques enable a 7 GS/s operation with a spurious-free dynamic range better than 32dBc over the full Nyquist bandwidth. The worst case narrowband SFDR is 42dBc. This system consumes 87.9mW/(GS/s) from a 1.2V power supply when the RSTC-DEM method is enabled, resulting in a FoM of 458.9GS/s·2^(SFDR/6)/W. A proof-of-concept chip with an active area of only 0.22mm² was measured in prototypes encapsulated in a 144-pins low profile quad flat package.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E101.C.206/_p

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@ARTICLE{e101-c_4_206,
author={Abdel MARTINEZ ALONSO, Masaya MIYAHARA, Akira MATSUZAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 7GS/s Complete-DDFS-Solution in 65nm CMOS},
year={2018},
volume={E101-C},
number={4},
pages={206-217},
abstract={A 7GS/s complete-DDFS-solution featuring a two-times interleaved RDAC with 1.2Vpp-diff output swing was fabricated in 65nm CMOS. The frequency tuning and amplitude resolutions are 24-bits and 10-bits respectively. The RDAC includes a mixed-signal, high-speed architecture for random swapping thermometer coding dynamic element matching that improves the narrowband SFDR up to 8dB for output frequencies below 1.85GHz. The proposed techniques enable a 7 GS/s operation with a spurious-free dynamic range better than 32dBc over the full Nyquist bandwidth. The worst case narrowband SFDR is 42dBc. This system consumes 87.9mW/(GS/s) from a 1.2V power supply when the RSTC-DEM method is enabled, resulting in a FoM of 458.9GS/s·2^(SFDR/6)/W. A proof-of-concept chip with an active area of only 0.22mm² was measured in prototypes encapsulated in a 144-pins low profile quad flat package.},
keywords={},
doi={10.1587/transele.E101.C.206},
ISSN={1745-1353},
month={April},}

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TY - JOUR
TI - A 7GS/s Complete-DDFS-Solution in 65nm CMOS
T2 - IEICE TRANSACTIONS on Electronics
SP - 206
EP - 217
AU - Abdel MARTINEZ ALONSO
AU - Masaya MIYAHARA
AU - Akira MATSUZAWA
PY - 2018
DO - 10.1587/transele.E101.C.206
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E101-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2018
AB - A 7GS/s complete-DDFS-solution featuring a two-times interleaved RDAC with 1.2Vpp-diff output swing was fabricated in 65nm CMOS. The frequency tuning and amplitude resolutions are 24-bits and 10-bits respectively. The RDAC includes a mixed-signal, high-speed architecture for random swapping thermometer coding dynamic element matching that improves the narrowband SFDR up to 8dB for output frequencies below 1.85GHz. The proposed techniques enable a 7 GS/s operation with a spurious-free dynamic range better than 32dBc over the full Nyquist bandwidth. The worst case narrowband SFDR is 42dBc. This system consumes 87.9mW/(GS/s) from a 1.2V power supply when the RSTC-DEM method is enabled, resulting in a FoM of 458.9GS/s·2^(SFDR/6)/W. A proof-of-concept chip with an active area of only 0.22mm² was measured in prototypes encapsulated in a 144-pins low profile quad flat package.
ER -