An Analysis and Design Methodology of Resistor-Based Phase Error Averaging for Multiphase Generation

Young-Sang KIM; Yunjae SUH; Hong-June PARK; Jae-Yoon SIM

doi:10.1587/transele.E93.C.1662

An Analysis and Design Methodology of Resistor-Based Phase Error Averaging for Multiphase Generation

Young-Sang KIM, Yunjae SUH, Hong-June PARK, Jae-Yoon SIM

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This paper presents a quantitative analysis and design methodology of resistor-based phase error averaging scheme for precise multiphase generation. Unlike the previously reported works stating that more averaging simply achieves better linearity, the proposed analysis leads to the existence of the optimum number of averaging contributions by including the effect of the signal transition time. The developed model shows a good agreement with a Monte-Carlo circuit simulation. A test PLL with a 32-phase two-dimensional ring VCO, implemented in a 0.18 µm CMOS, generates monotonous 32 phases with the best linearity performance, showing an INL of +0.27/-1.0 LSB and a DNL of +0.37/-0.27 LSB at 1.2 GHz, and an INL of +0.23/-1.57 LSB and a DNL of +0.44/-0.44 LSB at 1.6 GHz.

Publication: IEICE TRANSACTIONS on Electronics Vol.E93-C No.12 pp.1662-1669

Publication Date: 2010/12/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E93.C.1662

Type of Manuscript: PAPER

Category: Electronic Circuits

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Young-Sang KIM, Yunjae SUH, Hong-June PARK, Jae-Yoon SIM, "An Analysis and Design Methodology of Resistor-Based Phase Error Averaging for Multiphase Generation" in IEICE TRANSACTIONS on Electronics, vol. E93-C, no. 12, pp. 1662-1669, December 2010, doi: 10.1587/transele.E93.C.1662.
Abstract: This paper presents a quantitative analysis and design methodology of resistor-based phase error averaging scheme for precise multiphase generation. Unlike the previously reported works stating that more averaging simply achieves better linearity, the proposed analysis leads to the existence of the optimum number of averaging contributions by including the effect of the signal transition time. The developed model shows a good agreement with a Monte-Carlo circuit simulation. A test PLL with a 32-phase two-dimensional ring VCO, implemented in a 0.18 µm CMOS, generates monotonous 32 phases with the best linearity performance, showing an INL of +0.27/-1.0 LSB and a DNL of +0.37/-0.27 LSB at 1.2 GHz, and an INL of +0.23/-1.57 LSB and a DNL of +0.44/-0.44 LSB at 1.6 GHz.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.1662/_p

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@ARTICLE{e93-c_12_1662,
author={Young-Sang KIM, Yunjae SUH, Hong-June PARK, Jae-Yoon SIM, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Analysis and Design Methodology of Resistor-Based Phase Error Averaging for Multiphase Generation},
year={2010},
volume={E93-C},
number={12},
pages={1662-1669},
abstract={This paper presents a quantitative analysis and design methodology of resistor-based phase error averaging scheme for precise multiphase generation. Unlike the previously reported works stating that more averaging simply achieves better linearity, the proposed analysis leads to the existence of the optimum number of averaging contributions by including the effect of the signal transition time. The developed model shows a good agreement with a Monte-Carlo circuit simulation. A test PLL with a 32-phase two-dimensional ring VCO, implemented in a 0.18 µm CMOS, generates monotonous 32 phases with the best linearity performance, showing an INL of +0.27/-1.0 LSB and a DNL of +0.37/-0.27 LSB at 1.2 GHz, and an INL of +0.23/-1.57 LSB and a DNL of +0.44/-0.44 LSB at 1.6 GHz.},
keywords={},
doi={10.1587/transele.E93.C.1662},
ISSN={1745-1353},
month={December},}

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TY - JOUR
TI - An Analysis and Design Methodology of Resistor-Based Phase Error Averaging for Multiphase Generation
T2 - IEICE TRANSACTIONS on Electronics
SP - 1662
EP - 1669
AU - Young-Sang KIM
AU - Yunjae SUH
AU - Hong-June PARK
AU - Jae-Yoon SIM
PY - 2010
DO - 10.1587/transele.E93.C.1662
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2010
AB - This paper presents a quantitative analysis and design methodology of resistor-based phase error averaging scheme for precise multiphase generation. Unlike the previously reported works stating that more averaging simply achieves better linearity, the proposed analysis leads to the existence of the optimum number of averaging contributions by including the effect of the signal transition time. The developed model shows a good agreement with a Monte-Carlo circuit simulation. A test PLL with a 32-phase two-dimensional ring VCO, implemented in a 0.18 µm CMOS, generates monotonous 32 phases with the best linearity performance, showing an INL of +0.27/-1.0 LSB and a DNL of +0.37/-0.27 LSB at 1.2 GHz, and an INL of +0.23/-1.57 LSB and a DNL of +0.44/-0.44 LSB at 1.6 GHz.
ER -