Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design

Li-Rong WANG; Ming-Hsien TU; Shyh-Jye JOU; Chung-Len LEE

doi:10.1587/transele.E94.C.1112

Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design

Li-Rong WANG, Ming-Hsien TU, Shyh-Jye JOU, Chung-Len LEE

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This paper presents a well-structured modified Booth encoding (MBE) multiplier which is applied in the design of a reconfigurable multiply-accumulator (MAC) core. The multiplier adopts an improved Booth encoder and selector to achieve an extra-row-removal and uses a hybrid approach in the two's complementation circuit to reduce the area and improve the speed. The multiplier is used to form a 32-bit reconfigurable MAC core which can be flexibly configured to execute one 3232, two 1616 or four 88 signed multiply-accumulation. Experimentally, when implemented with a 130 nm CMOS single-V_t standard cell library, the multiplier achieved a 15.8% area saving and 11.7% power saving over the classical design, and the reconfigurable MAC achieved a 4.2% area and a 7.4% power saving over the MAC design published so far if implemented with a mixed-V_t standard cell library.

Publication: IEICE TRANSACTIONS on Electronics Vol.E94-C No.6 pp.1112-1119

Publication Date: 2011/06/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E94.C.1112

Type of Manuscript: PAPER

Category: Electronic Circuits

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Li-Rong WANG, Ming-Hsien TU, Shyh-Jye JOU, Chung-Len LEE, "Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design" in IEICE TRANSACTIONS on Electronics, vol. E94-C, no. 6, pp. 1112-1119, June 2011, doi: 10.1587/transele.E94.C.1112.
Abstract: This paper presents a well-structured modified Booth encoding (MBE) multiplier which is applied in the design of a reconfigurable multiply-accumulator (MAC) core. The multiplier adopts an improved Booth encoder and selector to achieve an extra-row-removal and uses a hybrid approach in the two's complementation circuit to reduce the area and improve the speed. The multiplier is used to form a 32-bit reconfigurable MAC core which can be flexibly configured to execute one 3232, two 1616 or four 88 signed multiply-accumulation. Experimentally, when implemented with a 130 nm CMOS single-V_t standard cell library, the multiplier achieved a 15.8% area saving and 11.7% power saving over the classical design, and the reconfigurable MAC achieved a 4.2% area and a 7.4% power saving over the MAC design published so far if implemented with a mixed-V_t standard cell library.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.1112/_p

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@ARTICLE{e94-c_6_1112,
author={Li-Rong WANG, Ming-Hsien TU, Shyh-Jye JOU, Chung-Len LEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design},
year={2011},
volume={E94-C},
number={6},
pages={1112-1119},
abstract={This paper presents a well-structured modified Booth encoding (MBE) multiplier which is applied in the design of a reconfigurable multiply-accumulator (MAC) core. The multiplier adopts an improved Booth encoder and selector to achieve an extra-row-removal and uses a hybrid approach in the two's complementation circuit to reduce the area and improve the speed. The multiplier is used to form a 32-bit reconfigurable MAC core which can be flexibly configured to execute one 3232, two 1616 or four 88 signed multiply-accumulation. Experimentally, when implemented with a 130 nm CMOS single-V_t standard cell library, the multiplier achieved a 15.8% area saving and 11.7% power saving over the classical design, and the reconfigurable MAC achieved a 4.2% area and a 7.4% power saving over the MAC design published so far if implemented with a mixed-V_t standard cell library.},
keywords={},
doi={10.1587/transele.E94.C.1112},
ISSN={1745-1353},
month={June},}

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TY - JOUR
TI - Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design
T2 - IEICE TRANSACTIONS on Electronics
SP - 1112
EP - 1119
AU - Li-Rong WANG
AU - Ming-Hsien TU
AU - Shyh-Jye JOU
AU - Chung-Len LEE
PY - 2011
DO - 10.1587/transele.E94.C.1112
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2011
AB - This paper presents a well-structured modified Booth encoding (MBE) multiplier which is applied in the design of a reconfigurable multiply-accumulator (MAC) core. The multiplier adopts an improved Booth encoder and selector to achieve an extra-row-removal and uses a hybrid approach in the two's complementation circuit to reduce the area and improve the speed. The multiplier is used to form a 32-bit reconfigurable MAC core which can be flexibly configured to execute one 3232, two 1616 or four 88 signed multiply-accumulation. Experimentally, when implemented with a 130 nm CMOS single-V_t standard cell library, the multiplier achieved a 15.8% area saving and 11.7% power saving over the classical design, and the reconfigurable MAC achieved a 4.2% area and a 7.4% power saving over the MAC design published so far if implemented with a mixed-V_t standard cell library.
ER -