A 120-GHz Transmitter and Receiver Chipset with 9-Gbps Data Rate Using 65-nm CMOS Technology

Ryuichi FUJIMOTO; Mizuki MOTOYOSHI; Kyoya TAKANO; Uroschanit YODPRASIT; Minoru FUJISHIMA

doi:10.1587/transele.E95.C.1154

A 120-GHz Transmitter and Receiver Chipset with 9-Gbps Data Rate Using 65-nm CMOS Technology

Ryuichi FUJIMOTO, Mizuki MOTOYOSHI, Kyoya TAKANO, Uroschanit YODPRASIT, Minoru FUJISHIMA

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The design and measured results of a 120-GHz transmitter and receiver chipset are described in this paper. A simple on-off keying (OOK) modulation is adopted for low power consumption. The proposed transmitter and receiver are fabricated using 65-nm CMOS technology. The current consumption of the transmitter and receiver are 19.2 mA and 48.2 mA respectively. A 9-Gbps PRBS is successfully transferred from the transmitter to the receiver with the bit error rate less than 10^-9.

Publication: IEICE TRANSACTIONS on Electronics Vol.E95-C No.7 pp.1154-1162

Publication Date: 2012/07/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E95.C.1154

Type of Manuscript: Special Section PAPER (Special Section on Recent Trends of Microwave Systems and Their Fundamental Technologies)

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Ryuichi FUJIMOTO, Mizuki MOTOYOSHI, Kyoya TAKANO, Uroschanit YODPRASIT, Minoru FUJISHIMA, "A 120-GHz Transmitter and Receiver Chipset with 9-Gbps Data Rate Using 65-nm CMOS Technology" in IEICE TRANSACTIONS on Electronics, vol. E95-C, no. 7, pp. 1154-1162, July 2012, doi: 10.1587/transele.E95.C.1154.
Abstract: The design and measured results of a 120-GHz transmitter and receiver chipset are described in this paper. A simple on-off keying (OOK) modulation is adopted for low power consumption. The proposed transmitter and receiver are fabricated using 65-nm CMOS technology. The current consumption of the transmitter and receiver are 19.2 mA and 48.2 mA respectively. A 9-Gbps PRBS is successfully transferred from the transmitter to the receiver with the bit error rate less than 10^-9.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.1154/_p

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@ARTICLE{e95-c_7_1154,
author={Ryuichi FUJIMOTO, Mizuki MOTOYOSHI, Kyoya TAKANO, Uroschanit YODPRASIT, Minoru FUJISHIMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 120-GHz Transmitter and Receiver Chipset with 9-Gbps Data Rate Using 65-nm CMOS Technology},
year={2012},
volume={E95-C},
number={7},
pages={1154-1162},
abstract={The design and measured results of a 120-GHz transmitter and receiver chipset are described in this paper. A simple on-off keying (OOK) modulation is adopted for low power consumption. The proposed transmitter and receiver are fabricated using 65-nm CMOS technology. The current consumption of the transmitter and receiver are 19.2 mA and 48.2 mA respectively. A 9-Gbps PRBS is successfully transferred from the transmitter to the receiver with the bit error rate less than 10^-9.},
keywords={},
doi={10.1587/transele.E95.C.1154},
ISSN={1745-1353},
month={July},}

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TY - JOUR
TI - A 120-GHz Transmitter and Receiver Chipset with 9-Gbps Data Rate Using 65-nm CMOS Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 1154
EP - 1162
AU - Ryuichi FUJIMOTO
AU - Mizuki MOTOYOSHI
AU - Kyoya TAKANO
AU - Uroschanit YODPRASIT
AU - Minoru FUJISHIMA
PY - 2012
DO - 10.1587/transele.E95.C.1154
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2012
AB - The design and measured results of a 120-GHz transmitter and receiver chipset are described in this paper. A simple on-off keying (OOK) modulation is adopted for low power consumption. The proposed transmitter and receiver are fabricated using 65-nm CMOS technology. The current consumption of the transmitter and receiver are 19.2 mA and 48.2 mA respectively. A 9-Gbps PRBS is successfully transferred from the transmitter to the receiver with the bit error rate less than 10^-9.
ER -